Proceedings of the 36th Design Automation Conference
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter

Mary Jane Irwin
Proceedings of the 36th Design Automation Conference
DAC, 1999.

SYS
DBLP
Scholar
Full names Links ISxN
@proceedings{DAC-1999,
	acmid         = "309847",
	address       = "New Orleans, Louisiana, USA",
	editor        = "Mary Jane Irwin",
	publisher     = "{ACM Press}",
	title         = "{Proceedings of the 36th Design Automation Conference}",
	year          = 1999,
}

Contents (176 items)

DAC-1999-LiWW #approach #equation #generative #modelling #performance
An Efficient Lyapunov Equation-Based Approach for Generating Reduced-Order Models of Interconnect (JRL, FW, JW), pp. 1–6.
DAC-1999-ChenW #approximate #bound #fault
Error Bounded Padé Approximation via Bilinear Conformal Transformation (CPC, DFW), pp. 7–12.
DAC-1999-GunupudiN #using
Model-Reduction of Nonlinear Circuits Using Krylov-Space Techniques (PKG, MSN), pp. 13–16.
DAC-1999-Sheehan #equation #named #order #performance #reduction #using
ENOR: Model Order Reduction of RLC Circuits Using Nodal Equations for Efficient Factorization (BNS), pp. 17–21.
DAC-1999-PrasadCK #question #why
Why is ATPG Easy? (MRP, PC, KK), pp. 22–28.
DAC-1999-DrechslerG #bound #using
Using Lower Bounds During Dynamic BDD Minimization (RD, WG), pp. 29–32.
DAC-1999-QuWP #problem
Optimization-Intensive Watermarking Techniques for Decision Problems (GQ, JLW, MP), pp. 33–36.
DAC-1999-DasdanIG #algorithm #performance #problem
Efficient Algorithms for Optimum Cycle Mean and Optimum Cost to Time Ratio Problems (AD, SI, RKG), pp. 37–42.
DAC-1999-Gajski #design
IP-based Design Methodology (DG), p. 43.
DAC-1999-ChouOHPB #design #distributed #embedded #framework #named
ipChinook: an Integrated IP-based Design Framework for Distributed Embedded Systems (PHC, RBO, KH, KP, GB), pp. 44–49.
DAC-1999-DalpassoBB #design #distributed #simulation
Virtual Simulation of Distributed IP-based Designs (MD, AB, LB), pp. 50–55.
DAC-1999-LakshminarayanaRKJD #optimisation #performance
Common-Case Computation: A High-Level Technique for Power and Performance Optimization (GL, AR, KSK, NKJ, SD), pp. 56–61.
DAC-1999-YehKSW #design #layout #using
Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs (CWY, YSK, SJS, JSW), pp. 62–67.
DAC-1999-YehCCJ #design
Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications (CWY, MCC, SCC, WBJ), pp. 68–71.
DAC-1999-SundararajanP #power management #synthesis #using
Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages (VS, KKP), pp. 72–75.
DAC-1999-CamposanoKFSL #design #embedded
HW and SW in Embedded System Design: Loveboat, Shipwreck, or Ships Passing in the Night (RC, KK, JF, ALSV, JL), pp. 76–77.
DAC-1999-TanSLLY #linear #network #optimisation #sequence
Reliability-Constrained Area Optimization of VLSI Power/Ground Networks via Sequence of Linear Programmings (XDT, CJRS, DL, JCL, LPY), pp. 78–83.
DAC-1999-HuS #named
FAR-DS: Full-Plane AWE Routing with Driver Sizing (JH, SSS), pp. 84–89.
DAC-1999-JiangJC #optimisation #performance
Noise-Constrained Performance Optimization by Simultaneous Gate and Wire Sizing Based on Lagrangian Relaxation (IHRJ, JYJ, YWC), pp. 90–95.
DAC-1999-ZhouWLA #strict
Simultaneous Routing and Buffer Insertion with Restrictions on Buffer Locations (HZ, DFW, IML, AA), pp. 96–99.
DAC-1999-SaxenaL #using
Crosstalk Minimization Using Wire Perturbations (PS, CLL), pp. 100–103.
DAC-1999-BrunvandNY #design #interface
Practical Advances in Asynchronous Design and in Asynchronous/Synchronous Interfaces (EB, SMN, KYY), pp. 104–109.
DAC-1999-KondratyevCKLY #automation #optimisation #synthesis
Automatic Synthesis and Optimization of Partially Specified Asynchronous Systems (AK, JC, MK, LL, AY), pp. 110–115.
DAC-1999-StevensRBCGKR #performance
CAD Directions for High Performance Asynchronous Circuits (KSS, SR, SMB, JC, RG, MK, MR), pp. 116–121.
DAC-1999-Henkel #approach #clustering #embedded #hardware #power management
A Low Power Hardware/Software Partitioning Approach for Core-Based Embedded Systems (JH), pp. 122–127.
DAC-1999-BeniniMMPS #communication #interface #power management #synthesis
Synthesis of Low-Overhead Interfaces for Power-Efficient Communication over Wide Buses (LB, AM, EM, MP, RS), pp. 128–133.
DAC-1999-ShinC #realtime #scheduling
Power Conscious Fixed Priority Scheduling for Hard Real-Time Systems (YS, KC), pp. 134–139.
DAC-1999-ShiueC #embedded #memory management #power management
Memory Exploration for Low Power, Embedded Systems (WTS, CC), pp. 140–145.
DAC-1999-Sharma #development #distributed
Distributed Application Development with Inferno (RS), pp. 146–150.
DAC-1999-StepnerRH #design #embedded #realtime #using
Embedded Application Design Using a Real-Time OS (DS, NR, DH), pp. 151–156.
DAC-1999-Arnold #architecture #flexibility #network
The Jini Architecture: Dynamic Services in a Flexible Network (KA), pp. 157–162.
DAC-1999-AbtsR #multi #scalability #using #verification
Verifying Large-Scale Multiprocessors Using an Abstract Verification Environment (DA, MR), pp. 163–168.
DAC-1999-ShenABHKGCH #functional #verification
Functional Verification of the Equator MAP1000 Microprocessor (JS, JAA, DB, TH, MK, GG, CcC, GH), pp. 169–174.
DAC-1999-UrY #architecture #generative #source code
Micro Architecture Coverage Directed Generation of Test Programs (SU, YY), pp. 175–180.
DAC-1999-ChangLPK #using #verification
Verification of a Microprocessor Using Real World Applications (YSC, SL, ICP, CMK), pp. 181–184.
DAC-1999-CampenhoutMH #design #generative #pipes and filters #testing #verification
High-Level Test Generation for Design Verification of Pipelined Microprocessors (DVC, TNM, JPH), pp. 185–188.
DAC-1999-FournierKL #architecture #validation
Developing an Architecture Validation Suite: Applicaiton to the PowerPC Architecture (LF, AK, ML), pp. 189–194.
DAC-1999-Freund #algorithm #modelling #simulation
Passive Reduced-Order Models for Interconnect Simulation and Their Computation via Krylov-Subspace Algorithms (RWF), pp. 195–200.
DAC-1999-LiuPS #analysis
Model Order-Reduction of RC(L) Interconnect Including Variational Analysis (YL, LTP, AJS), pp. 201–206.
DAC-1999-CoelhoPS #algorithm #approximate #generative #robust
Robust Rational Function Approximation Algorithm for Model Generation (CPC, JRP, LMS), pp. 207–212.
DAC-1999-Bergamaschi #behaviour #graph #logic #network #synthesis
Behavioral Network Graph: Unifying the Domains of High-Level and Logic Synthesis (RAB), pp. 213–218.
DAC-1999-ZhuG #scheduling #synthesis
Soft Scheduling in High Level Synthesis (JZ, DG), pp. 219–224.
DAC-1999-PerkowskiMGBM #algorithm #evaluation #graph #performance
Graph Coloring Algorithms for Fast Evaluation of Curtis Decompositions (MAP, RM, SG, MB, AM), pp. 225–230.
DAC-1999-LiuPF #performance #scheduling
Maximizing Performance by Retiming and Clock Skew Scheduling (XL, MCP, EGF), pp. 231–236.
DAC-1999-EcklMZL #approach #multi
A Practical Approach to Multiple-Class Retiming (KE, JCM, PZ, CL), pp. 237–242.
DAC-1999-Pan #integration
Performance-Driven Integration of Retiming and Resynthesis (PP), pp. 243–246.
DAC-1999-BeniniMMOP #algorithm #approximate #component #kernel #optimisation
Kernel-Based Power Optimization of RTL Components: Exact and Approximate Extraction Algorithms (LB, GDM, EM, GO, MP), pp. 247–252.
DAC-1999-Fisher #embedded
Customized Instruction-Sets for Embedded Processors (JAF), pp. 253–257.
DAC-1999-Harbison #hardware #trade-off
System-Level Hardware/Software Trade-offs (SPH), pp. 258–259.
DAC-1999-SuWL #interactive
A Timing-Driven Soft-Macro Resynthesis Method in Interaction with Chip Floorplanning (HPS, ACHW, YLL), pp. 262–267.
DAC-1999-GuoCY #representation
An O-Tree Representation of Non-Slicing Floorplan and Its Applications (PNG, CKC, TY), pp. 268–273.
DAC-1999-BalasaL #layout #representation #using
Module Placement for Analog Layout Using the Sequence-Pair Representation (FB, KL), pp. 274–279.
DAC-1999-Grajcar #algorithm #multi #scheduling #search-based
Genetic List Scheduling Algorithm for Scheduling and Allocation on a Loosely Coupled Heterogeneous Multiprocessor System (MG), pp. 280–285.
DAC-1999-ParkC #scheduling
Performance-Driven Scheduling with Bit-Level Chaining (SP, KC), pp. 286–291.
DAC-1999-HaynalB #component #scheduling
A Model for Scheduling Protocol-Constrained Components and Environments (SH, FB), pp. 292–295.
DAC-1999-SantosJ #order #performance
A Reordering Technique for Efficient Code Motion (LCVdS, JAGJ), pp. 296–299.
DAC-1999-HoskoteKHZ #estimation #model checking
Coverage Estimation for Symbolic Model Checking (YVH, TK, PHH, XZ), pp. 300–305.
DAC-1999-CabodiCQ #process #traversal
Improving Symbolic Traversals by Means of Activity Profiles (GC, PC, SQ), pp. 306–311.
DAC-1999-GovindarajuDB #approximate #reachability #using
Improved Approximate Reachability Using Auxiliary State Variables (SGG, DLD, JPB), pp. 312–316.
DAC-1999-BiereCCFZ #model checking #satisfiability #using
Symbolic Model Checking Using SAT Procedures instead of BDDs (AB, AC, EMC, MF, YZ), pp. 317–320.
DAC-1999-KinLMP #design #performance
Power Efficient Mediaprocessors: Design Space Exploration (JK, CL, WHMS, MP), pp. 321–326.
DAC-1999-VandecappelleMBCV #design #feedback #memory management #multi #using
Global Multimedia System Design Exploration Using Accurate Memory Organization Feedback (AV, MM, EB, FC, DV), pp. 327–332.
DAC-1999-NachtergaeleVPLBB #implementation #scalability #visual notation
Implementation of a Scalable MPEG-4 Wavelet-Based Visual Texture Compression System (LN, BV, MP, GL, JB, IB), pp. 333–336.
DAC-1999-SchaumontCVE #automation
A 10 Mbit/s Upstream Cable Modem with Automatic equalization (PS, RC, SV, ME), pp. 337–340.
DAC-1999-KarypisK #clustering #multi
Multilevel k-way Hypergraph Partitioning (GK, VK), pp. 343–348.
DAC-1999-CaldwellKKM #clustering #development #heuristic
Hypergraph Partitioning for VLSI CAD: Methodology for Heuristic Development, Experimentation and Reporting (AEC, ABK, AAK, ILM), pp. 349–354.
DAC-1999-CaldwellKM #clustering
Hypergraph Partitioning with Fixed Vertices (AEC, ABK, ILM), pp. 355–359.
DAC-1999-HurL #clustering #framework #linear
Relaxation and Clustering in a Local Search Framework: Application to Linear Placement (SWH, JL), pp. 360–366.
DAC-1999-RoyBB #algorithm #constraints
An Approxmimate Algorithm for Delay-Constraint Technology Mapping (SR, KPB, PB), pp. 367–372.
DAC-1999-CongHX #performance
Technology Mapping for FPGAs with Nonuniform Pin Delays and Fast Interconnections (JC, YYH, SX), pp. 373–378.
DAC-1999-PatraN #automation #power management #synthesis
Automated Phase Assignment for the Synthesis of Low Power Domino Circuits (PP, UN), pp. 379–384.
DAC-1999-GanaiAK #simulation
Enhancing Simulation with BDDs and ATPG (MKG, AA, AK), pp. 385–390.
DAC-1999-BertaccoDQ #simulation
Cycle-Based Symbolic Simulation of Gate-Level Synchronous Circuits (VB, MD, SQ), pp. 391–396.
DAC-1999-VelevB #pipes and filters #similarity #verification
Exploiting Positive Equality and Partial Non-Consistency in the Formal Verification of Pipelined Microprocessors (MNV, REB), pp. 397–401.
DAC-1999-AagaardJS #constraints #parametricity
Parametric Representations of Boolean Constraints (MA, RBJ, CJHS), pp. 402–407.
DAC-1999-InacioSNRTTK #benchmark #metric
Vertical Benchmarks for CAD (CI, HS, DN, AR, DET, YT, BK), pp. 408–413.
DAC-1999-HuGRQ #design #framework
A Framework for User Assisted Design Space Exploration (XH, GWG, SR, GQ), pp. 414–419.
DAC-1999-ClementHLRCP #design #multi #performance #prototype
Fast Prototyping: A System Design Flow Applied to a Complex System-on-Chip Multiprocessor Design (BC, RH, EL, BR, PC, FP), pp. 420–424.
DAC-1999-NotbauerANR #design #embedded #multi #verification
Verification and Management of a Multimillion-Gate Embedded Core Design (JN, TWA, GN, SR), pp. 425–428.
DAC-1999-FranzonBFMPSW #how #question
Parasitic Extraction Accuracy — How Much is Enough? (PDF, MB, AF, SM, RP, RCS, MW), p. 429.
DAC-1999-WeiCRYD #design #power management
Mixed-Vth (MVT) CMOS Circuit Design Methodology for Low Power Applications (LW, ZC, KR, YY, VD), pp. 430–435.
DAC-1999-SirichotiyakulEOZDPB #power management
Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.
DAC-1999-JohnsonSR #performance #using
Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS (MCJ, DS, KR), pp. 442–445.
DAC-1999-HashimotoOT #design #power management #reduction
A Practical Gate Resizing Technique Considering Glitch Reduction for Low Power Design (MH, HO, KT), pp. 446–451.
DAC-1999-ConnEMOSVW #optimisation #using
Gradient-Based Optimization of Custom Circuits Using a Static-Timing Formulation (ARC, IME, WWM, PRO, PNS, CV, CBW), pp. 452–459.
DAC-1999-CongLW #clustering #optimisation #performance
Simultaneous Circuit Partitioning/Clustering with Retiming for Performance Optimization (JC, HL, CW), pp. 460–465.
DAC-1999-MukherjeeSML #layout #novel #synthesis
Wave Steering in YADDs: A Novel Non-Iterative Synthesis and Layout Technique (AM, RS, MMS, SIL), pp. 466–471.
DAC-1999-SalekLP #generative #independence #named #using
MERLIN: Semi-Order-Independent Hierarchical Buffered Routing Tree Generation Using Local Neighborhood Search (AHS, JL, MP), pp. 472–478.
DAC-1999-AlpertDQ
Buffer Insertion with Accurate Gate and Interconnect Delay Computation (CJA, AD, STQ), pp. 479–484.
DAC-1999-YimK #design
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design (JSY, CMK), pp. 485–490.
DAC-1999-KhatriMBOS #layout #novel
A Novel VLSI Layout Fabric for Deep Sub-Micron Applications (SPK, AM, RKB, RHJMO, ALSV), pp. 491–496.
DAC-1999-PomerleauFB #predict
Improved Selay Prediction for On-Chip Buses (RGP, PDF, GLB), pp. 497–501.
DAC-1999-ChenM #using
Noise-Aware Repeater Insertion and Wire-Sizing for On-Chip Interconnect Using Hierarchical Moment-Matching (CPC, NM), pp. 502–506.
DAC-1999-CongP #design #estimation
Interconnect Estimation and Dlanning for Deep Submicron Designs (JC, DZP), pp. 507–510.
DAC-1999-LavagnoS #design #named #specification
ECL: A Specification Environment for System-Level Design (LL, ES), pp. 511–516.
DAC-1999-RichterZETT #embedded #optimisation #representation #synthesis
Representation of Function Variants for Embedded System Optimization and Synthesis (KR, DZ, RE, LT, JT), pp. 517–522.
DAC-1999-BergmannH #named
Vex — A CAD Toolbox (JPB, MH), pp. 523–528.
DAC-1999-CarballoD #collaboration #constraints #design
Constraint Management for Collaborative Electronic Design (JAC, SWD), pp. 529–534.
DAC-1999-TauschW #multi #performance
A Multiscale Method for Fast Capacitance Extraction (JT, JKW), pp. 537–542.
DAC-1999-JandhyalaSBC #adaptation #performance
Efficient Capacitance Computation for Structures with Non-Uniform Adaptive Surface Meshes (VJ, SS, JEB, ZJC), pp. 543–548.
DAC-1999-LiTRK #modelling #simulation
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (TL, CHT, ER, SMK), pp. 549–554.
DAC-1999-QiuP #markov #power management #process
Dynamic Power Management Based on Continuous-Time Markov Decision Processes (QQ, MP), pp. 555–561.
DAC-1999-ChinosiZG #clustering #parallel #simulation
Parallel Mixed-Level Power Simulation Based on Spatio-Temporal Circuit Partitioning (MC, RZ, CG), pp. 562–567.
DAC-1999-ErcegovacKP #behaviour #multi #optimisation #power management #precise #synthesis #using
Low-Power Behavioral Synthesis Optimization Using Multiple Precision Arithmetic (MDE, DK, MP), pp. 568–573.
DAC-1999-GeistBASNFHLKB #verification
A Methodology for the Verification of a “System on Chip” (DG, GB, TA, MS, YN, MF, KH, AL, DK, SB), pp. 574–579.
DAC-1999-HuangL #embedded #named
ICEBERG: An Embedded In-Circuit Emulator Synthesizer for Microcontrollers (IJH, TAL), pp. 580–585.
DAC-1999-PapachristouMN #testing
Microprocessor Based Testing for Core-Based System on Chip (CAP, FM, MN), pp. 586–591.
DAC-1999-KapadiaH #automation #clustering #convergence #design #standard #using
Using Partitioning to Help Convergence in the Standard-Cell Design Automation Methodology (HK, MH), pp. 592–597.
DAC-1999-MoussaSSDPCGJ #behaviour #design
Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper (IM, ZS, RS, MDN, MP, SC, LG, AAJ), pp. 598–603.
DAC-1999-KirovskiP #behaviour #synthesis
Engineering Change: Methodology and Applications to Behavioral and System Synthesis (DK, MP), pp. 604–609.
DAC-1999-DeHonW #automation #configuration management #design #what #why
Reconfigurable Computing: What, Why, and Implications for Design Automation (AD, JW), pp. 610–615.
DAC-1999-KaulVGO #approach #automation #clustering #configuration management #synthesis
An Automated Temporal Partitioning and Loop Fission Approach for FPGA Based Reconfigurable Synthesis of DSP Applications (MK, RV, SG, IO), pp. 616–622.
DAC-1999-AdarioRB #architecture #configuration management #image
Dynamically Reconfigurable Architecture for Image Processor Applications (AMSA, ELR, SB), pp. 623–628.
DAC-1999-NarayanR #multi #simulation
Multi-Time Simulation of Voltage-Controlled Oscillators (ON, JSR), pp. 629–634.
DAC-1999-FengPNKW #approach #performance
Efficient Computation of Quasi-Periodic Circuit Operating Conditions via a Mixed Frequency/Time Approach (DF, JRP, KN, KSK, JW), pp. 635–640.
DAC-1999-NastovW
Time-Mapped Harmonic Balance (OJN, JW), pp. 641–646.
DAC-1999-TupuriKA #automation #constraints #functional #generative #testing #using
Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor (RST, AK, JAA), pp. 647–652.
DAC-1999-GuoRP #generative #named #using
Proptest: A Property Based Test Pattern Generator for Sequential Circuits Using Test Compaction (RG, SMR, IP), pp. 653–659.
DAC-1999-BoppanaMJFB #fault #multi
Multiple Error Diagnosis Based on Xlists (VB, RM, JJ, MF, PB), pp. 660–665.
DAC-1999-FallahAD #generative #simulation
Simulation Vector Generation from HDL Descriptions for Observability-Enhanced Statement Coverage (FF, PA, SD), pp. 666–671.
DAC-1999-Bening #logic #simulation
A Two-State Methodology for RTL Logic Simulation (LB), pp. 672–677.
DAC-1999-HansenNR #algorithm #approach #specification
An Approach for Extracting RT Timing Information to Annotate Algorithmic VHDL Specifications (CH, FN, WR), pp. 678–683.
DAC-1999-AbramoviciSS #configuration management #hardware #satisfiability #using
A Massively-Parallel Easily-Scalable Satisfiability Solver Using Reconfigurable Hardware (MA, JTdS, DGS), pp. 684–690.
DAC-1999-KocanS #configuration management #fault #hardware
Dynamic Fault Diagnosis on Reconfigurable Hardware (FK, DGS), pp. 691–696.
DAC-1999-ZhuL #compilation #configuration management #hardware
Hardware Compilation for FPGA-Based Configurable Computing Machines (XZ, BL), pp. 697–702.
DAC-1999-Eaglesham
0.18m CMOS and Beyond (DJE), pp. 703–708.
DAC-1999-ChuangP #design #perspective
SOI Digital CMOS VLSI — a Design Perspective (CTC, RP), pp. 709–714.
DAC-1999-IsmailFN
Equivalent Elmore Delay for RLC Trees (YII, EGF, JLN), pp. 715–720.
DAC-1999-IsmailF
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits (YII, EGF), pp. 721–724.
DAC-1999-TabbaraBN #constraints #trade-off
Retiming for DSM with Area-Delay Trade-Offs and Delay Constraints (AT, RKB, ARN), pp. 725–730.
DAC-1999-YalcinMPBS #analysis #functional
Functional Timing Analysis for IP Characterization (HY, MM, RP, CB, KAS), pp. 731–736.
DAC-1999-RaimiA #detection
Detecting False Timing Paths: Experiments on PowerPC Microprocessors (RR, JAA), pp. 737–741.
DAC-1999-KimHT #on the #self #synthesis
On ILP Formulations for Built-In Self-Testable Data Path Synthesis (HBK, DSH, TT), pp. 742–747.
DAC-1999-TsaiCB #quality #using
Improving the Test Quality for Scan-Based BIST Using a General Test Application Scheme (HCT, KTC, SB), pp. 748–753.
DAC-1999-PomeranzR #generative #sequence #testing
Built-In Test Sequence Generation for Synchronous Sequential Circuits Based on Loading and Expansion of Test Subsequences (IP, SMR), pp. 754–759.
DAC-1999-JiangC #analysis #performance #power management
Analysis of Performance Impact Caused by Power Supply Noise in Deep Submicron Devices (YMJ, KTC), pp. 760–765.
DAC-1999-YimBK
A Floorplan-Based Planning Methodology for Power and Clock Distribution in ASICs (JSY, SOB, CMK), pp. 766–771.
DAC-1999-HarjaniV #fault #parametricity
Digital Aetection of Analog Parametric Faults in SC Filters (RH, BV), pp. 772–777.
DAC-1999-WilkesH #design #hardware #interface
Application of High Level Interface-Based Design to Telecommunications System Hardware (DW, MMKH), pp. 778–783.
DAC-1999-SchaumontCVEB #behaviour #hardware #reuse
Hardware Reuse at the Behavioral Level (PS, RC, SV, ME, IB), pp. 784–789.
DAC-1999-KuhnRK #hardware #java #simulation
Description and Simulation of Hardware/Software Systems with Java (TK, WR, UK), pp. 790–793.
DAC-1999-FleischmannBK #embedded #java #prototype
Java Driven Codesign and Prototyping of Networked Embedded Systems (JF, KB, RK), pp. 794–797.
DAC-1999-KahngP #design
Subwavelength Lithography and Its Potential Impact on Design and EDA (ABK, YCP), pp. 799–804.
DAC-1999-SgroiL #embedded #petri net #synthesis #using
Synthesis of Embedded Software Using Free-Choice Petri Nets (MS, LL), pp. 805–810.
DAC-1999-ZhaoM #array #estimation #memory management
Exact Memory Size Estimation for Array Computations without Loop Unrolling (YZ, SM), pp. 811–816.
DAC-1999-BashfordL #constraints #fixpoint
Constraint Driven Code Selection for Fixed-Point DSPs (SB, RL), pp. 817–822.
DAC-1999-PegatoquetGAB #agile #development
Rapid Development of Optimized DSP Code from a High Level Description Through Software Estimations (AP, EG, MA, LB), pp. 823–826.
DAC-1999-KalavadeOAS #multi
Software Environment for a Multiprocessor DSP (AK, JO, BDA, KJS), pp. 827–830.
DAC-1999-LachMP #multi #robust
Robust FPGA Intellectual Property Protection Through Multiple Small Watermarks (JL, WHMS, MP), pp. 831–836.
DAC-1999-Oliveira #design #robust
Robust Techniques for Watermarking Sequential Circuit Designs (ALO), pp. 837–842.
DAC-1999-CaldwellCKMPQW #design #effectiveness
Effective Iterative Techniques for Fingerprinting Design IP (AEC, HJC, ABK, SM, MP, GQ, JLW), pp. 843–848.
DAC-1999-HongP #behaviour #synthesis
Behavioral Synthesis Techniques for Intellectual Property Protection (IH, MP), pp. 849–854.
DAC-1999-GoodmanCD #design #embedded #encryption #implementation #scalability
Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC Converter (JG, AC, APD), pp. 855–860.
DAC-1999-PedramW #design
Design Considerations for Battery-Powered Electronics (MP, QW), pp. 861–866.
DAC-1999-SimunicBM #embedded #energy #simulation
Cycle-Accurate Simulation of Energy Consumption in Embedded Systems (TS, LB, GDM), pp. 867–872.
DAC-1999-HemaniMKPONOEL #design #power management #using
Lowering Power Consumption in Clock by Using Globally Asynchronous Locally Synchronous Design Style (AH, TM, SK, AP, TO, PN, , PE, DL), pp. 873–878.
DAC-1999-KurzwegLMMPC
A CAD Tool for Optical MEMS (TPK, SPL, PJM, JAM, KRP, DMC), pp. 879–884.
DAC-1999-BanerjeeMSH #on the
On Thermal Effects in Deep Sub-Micron VLSI Interconnects (KB, AM, ALSV, CH), pp. 885–891.
DAC-1999-AllenBS
Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology (DA, DB, BS), pp. 892–897.
DAC-1999-KonduriC #collaboration #design #distributed #framework
A Framework for Collaborative and Distributed Web-Based Design (GK, AC), pp. 898–903.
DAC-1999-RestleRW #design #performance
Dealing with Inductance in High-Speed Chip Design (PR, AER, SGW), pp. 904–909.
DAC-1999-KamonMMSW #3d #analysis #modelling
Interconnect Analysis: From 3-D Structures to Circuit Models (MK, NAM, YM, LMS, JW), pp. 910–914.
DAC-1999-BeattieP #analysis #modelling
IC Analyses Including Extracted Inductance Models (MWB, LTP), pp. 915–920.
DAC-1999-Morton #multi
On-Chip Inductance Issues in Multiconductor Systems (SVM), pp. 921–926.
DAC-1999-HadjiyiannisRD #architecture #evaluation #performance
A Methodology for Accurate Performance Evaluation in Architecture Exploration (GH, PR, SD), pp. 927–932.
DAC-1999-PeesHZM #architecture #modelling #named #programmable
LISA — Machine Description Language for Cycle-Accurate Models of Programmable DSP Architectures (SP, AH, VZ, HM), pp. 933–938.
DAC-1999-ChoiYLPK #design #embedded
Exploiting Intellectual Properties in ASIP Designs for Embedded DSP Software (HC, JHY, JYL, ICP, CMK), pp. 939–944.
DAC-1999-KrasnickiPRC #named #performance #synthesis
MAELSTROM: Efficient Simulation-Based Synthesis for Custom Analog Cells (MK, RP, RAR, LRC), pp. 945–950.
DAC-1999-DoboliNDGV #behaviour #design #synthesis #using
Behavioral Synthesis of Analog Systems Using Two-layered Design Space Exploration (AD, ANA, NRD, SG, RV), pp. 951–957.
DAC-1999-DaemsGS #analysis #complexity #reduction
Circuit Complexity Reduction for Symbolic Analysis of Analog Integrated Circuits (WD, GGEG, WMCS), pp. 958–963.
DAC-1999-GuerraFTSTZ #integration #modelling
Cycle and Phase Accurate DSP Modeling and Integration for HW/SW Co-Verification (LMG, JF, DT, CS, BT, VZ), pp. 964–969.
DAC-1999-BenjaminGHMSW #case study #generative #testing
A Study in Coverage-Driven Test Generation (MB, DG, AH, GM, RS, YW), pp. 970–975.
DAC-1999-JiangV #energy #using
IC Test Using the Energy Consumption Ratio (WJ, BV), pp. 976–981.
DAC-1999-YueW #design
Design Strategy of On-Chip Inductors for Highly Integrated RF Systems (CPY, SSW), pp. 982–987.
DAC-1999-BelkFTBT #design #simulation
The Simulation and Design of Integrated Inductors (NRB, MRF, MT, AJB, KLT), pp. 988–993.
DAC-1999-HershensonMBL #geometry #optimisation #programming
Optimization of Inductor Circuits via Geometric Programming (MdMH, SSM, SPB, THL), pp. 994–998.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.