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Travelled to:
1 × Germany
Collaborated with:
K.Park T.Kim
Talks about:
buffer (2) synthesi (1) multipl (1) design (1) combin (1) adjust (1) power (1) delay (1) clock (1) alloc (1)

Person: Geunho Kim

DBLP DBLP: Kim:Geunho

Contributed to:

DATE 20142014

Wrote 1 papers:

DATE-2014-ParkKK #design #multi #synthesis
Mixed allocation of adjustable delay buffers combined with buffer sizing in clock tree synthesis of multiple power mode designs (KP, GK, TK), pp. 1–4.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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