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Travelled to:
1 × France
Collaborated with:
G.Yee C.Sechen
Talks about:
delay (2) technolog (1) implement (1) structur (1) domino (1) minim (1) logic (1) level (1) clock (1) use (1)

Person: Jovanka Ciric

DBLP DBLP: Ciric:Jovanka

Contributed to:

DATE 20002000

Wrote 1 papers:

DATE-2000-CiricYS #implementation #logic #using
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic (JC, GY, CS), pp. 277–282.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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