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Travelled to:
2 × Germany
3 × France
8 × USA
Collaborated with:
M.Rahman H.Tennakoon H.Tseng W.Swartz T.Serdar L.E.Liu T.Stanion A.L.Sangiovanni-Vincentelli J.Ciric G.Yee L.Scheffer M.Lefebvre D.Marple R.Afonso M.Vujkovic D.Wadkins B.Chappel J.Hogan A.Moore T.Nakamura G.A.Northrop A.Thakar
Talks about:
cell (7) rout (6) placement (5) synthesi (4) time (4) use (4) standard (3) librari (3) circuit (3) global (3)

Person: Carl Sechen

DBLP DBLP: Sechen:Carl

Contributed to:

DATE 20122012
DAC 20112011
DATE 20112011
DAC 20052005
DAC 20042004
DAC 20032003
DATE 20012001
DATE 20002000
DAC 19981998
DAC 19971997
ED&TC 19971997
DAC 19951995
DAC 19881988
DAC 19861986

Wrote 16 papers:

DATE-2012-RahmanS #power management
Post-synthesis leakage power minimization (MR, CS), pp. 99–104.
DAC-2011-RahmanATS #library #physics #reduction #synthesis
Power reduction via separate synthesis and physical libraries (MR, RA, HT, CS), pp. 627–632.
DATE-2011-RahmanTS #reduction
Power reduction via near-optimal library-based cell-size selection (MR, HT, CS), pp. 867–870.
DAC-2005-TennakoonS #modelling #performance
Efficient and accurate gate sizing with piecewise convex delay models (HT, CS), pp. 807–812.
DAC-2004-VujkovicWSS #performance
Efficient timing closure without timing driven placement and routing (MV, DW, WS, CS), pp. 268–273.
DAC-2003-SechenCHMNNT #library #named
Libraries: lifejacket or straitjacket (CS, BC, JH, AM, TN, GAN, AT), pp. 642–643.
DATE-2001-SerdarS #automation
Automatic datapath tile placement and routing (TS, CS), pp. 552–559.
DATE-2000-CiricYS #implementation #logic #using
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic (JC, GY, CS), pp. 277–282.
Timing and Crosstalk Driven Area Routing (HPT, LS, CS), pp. 378–381.
DAC-1997-LefebvreMS #future of #generative #physics #synthesis
The Future of Custom Cell Generation in Physical Synthesis (ML, DM, CS), pp. 446–451.
EDTC-1997-LiuS #graph #heuristic #multi #performance #using
Multi-layer chip-level global routing using an efficient graph-based Steiner tree heuristic (LCEL, CS), pp. 311–318.
EDTC-1997-TsengS #multi #standard #using
A gridless multi-layer router for standard cell circuits using CTM cells (HPT, CS), pp. 319–326.
DAC-1995-StanionS #synthesis
A Method for Finding Good Ashenhurst Decompositions and Its Application to FPGA Synthesis (TS, CS), pp. 60–64.
DAC-1995-SwartzS #scalability #standard
Timing Driven Placement for Large Standard Cell Circuits (WS, CS), pp. 211–215.
DAC-1988-Sechen #metaprogramming #using
Chip-Planning, Placement, and Global Routing of Macro/Custom Cell Integrated Circuits Using Simulated Annealing (CS), pp. 73–80.
DAC-1986-SechenS #standard
TimberWolf3.2: a new standard cell placement and global routing package (CS, ALSV), pp. 432–439.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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