BibSLEIGH — Proceedings of the Fifth Conference on Design, Automation and Test in Europe

Proceedings of the Fifth Conference on Design, Automation and Test in Europe
DATE, 2000.

SYS

@proceedings{DATE-2000,
	address       = "Paris, France",
	isbn          = "0-7695-0537-6",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Fifth Conference on Design, Automation and Test in Europe}",
	year          = 2000,
}

Contents (143 items)

DATE-2000-Leupers: Code Selection for Media Processors with SIMD Instructions (RL), pp. 4–8.
DATE-2000-GuptaGMC #analysis #program transformation #programmable: Analysis of High-Level Address Code Transformations for Programmable Processors (SG, RKG, MM, FC), pp. 9–13.
DATE-2000-KimLS #embedded #optimisation: Free MDD-Based Software Optimization Techniques for Embedded Systems (CK, LL, ALSV), pp. 14–18.
DATE-2000-LuCSMB #algorithm #comparison #power management: Quantitative Comparison of Power Management Algorithms (YHL, EYC, TS, GDM, LB), pp. 20–26.
DATE-2000-LajoloRDL #design #performance: Efficient Power Co-Estimation Techniques for System-on-Chip Design (ML, AR, SD, LL), pp. 27–34.
DATE-2000-BeniniCMMPS #estimation: A Discrete-Time Battery Model for High-Level Power Estimation (LB, GC, AM, EM, MP, RS), pp. 35–39.
DATE-2000-SchwenckerSGA #automation #bound #design: The Generalized Boundary Curve-A Common Method for Automatic Nominal Design and Design Centering of Analog Circuits (RS, FS, HEG, KA), pp. 42–47.
DATE-2000-GuerraRFR #analysis #approach #scalability: A Hierarchical Approach for the Symbolic Analysis of Large Analog Integrated Circuits (OG, ER, FVF, ÁRV), pp. 48–52.
DATE-2000-DessoukyLP #performance #synthesis: Layout-Oriented Synthesis of High Performance Analog Circuits (MD, MML, JP), pp. 53–57.
DATE-2000-GanesanV #array #programmable: Technology Mapping and Retargeting for Field-Programmable Analog Arrays (SG, RV), pp. 58–64.
DATE-2000-ZorianNMLSV #tutorial: Tutorial Statement (YZ, MN, PM, DYL, CWHS, KV), p. 66.
DATE-2000-Veelenturf #embedded #reliability #tool support: The Road to Better Reliability and Yield Embedded DfM Tools (KV), pp. 67–68.
DATE-2000-Zorian #embedded #scalability #trade-off: Yield Improvement and Repair Trade-Off for Large Embedded Memories (YZ), pp. 69–70.
DATE-2000-Strolenberg: Stay Away from Minimum Design-Rule Values (CWHS), pp. 71–72.
DATE-2000-VerkestKS #c++ #design #using: System Level Design Using C++ (DV, JK, FS), pp. 74–81.
DATE-2000-LyseckyVG #latency: Techniques for Reducing Read Latency of Core Bus Wrappers (RLL, FV, TG), pp. 84–91.
DATE-2000-VermeulenCMV #embedded #reuse: Formalized Three-Layer System-Level Reuse Model and Methodology for Embedded Data-Dominated Applications (FV, FC, HDM, DV), pp. 92–98.
DATE-2000-DalpassoBBF #design #distributed #fault #simulation: Virtual Fault Simulation of Distributed IP-Based Designs (MD, AB, LB, MF), pp. 99–103.
DATE-2000-TangWT #evaluation #performance #sequence: Fast Evaluation of Sequence Pair in Block Placement by Longest Common Subsequence Computation (XT, DFW, RT), pp. 106–111.
DATE-2000-Saab #algorithm #clustering #effectiveness #multi #performance: A New Effective And Efficient Multi-Level Partitioning Algorithm (YS), pp. 112–116.
DATE-2000-BrennerV #performance: Faster Optimal Single-Row Placement with Fixed Ordering (UB, JV), pp. 117–121.
DATE-2000-BouraiS #layout #optimisation: Layout Compaction for Yield Optimization via Critical Area Minimization (YB, CJRS), pp. 122–125.
DATE-2000-OzevBO #synthesis: Test Synthesis for Mixed-Signal SOC Paths (SO, IB, AO), pp. 128–133.
DATE-2000-SugiharaYD #analysis #approach: Analysis and Minimization of Test Time in a Combined BIST and External Test Approach (MS, HY, HD), pp. 134–140.
DATE-2000-BenabdenebiMM #configuration management #named #scalability: CAS-BUS: A Scalable and Reconfigurable Test Access Mechanism for Systems on a Chip (MB, WM, MM), pp. 141–145.
DATE-2000-ZivkovicTK #architecture #design: Design and Test Space Exploration of Transport-Triggered Architectures (VAZ, RJWTT, HGK), pp. 146–151.
DATE-2000-JantschB: Composite Signal Flow: A Computational Model Combining Events, Sampled Streams, and Vectors (AJ, PB), pp. 154–160.
DATE-2000-BjureusJ #control flow #named #specification: MASCOT: A Specification and Cosimulation Method Integrating Data and Control Flow (PB, AJ), pp. 161–168.
DATE-2000-JosephsF #interface #specification #synthesis: Delay-Insensitive Interface Specification and Synthesis (MBJ, DPF), pp. 169–173.
DATE-2000-ViglioneMPRZ: A 50 Mbit/s Iterative Turbo-Decoder (FV, GM, GP, MRR, MZ), pp. 176–180.
DATE-2000-GirolaPV: Smart Antenna Receiver Based on a Single Chip Solution for GSM/DCS Baseband Processing (UG, AP, DV), pp. 181–185.
DATE-2000-MurookaM #protocol: Protocol Stack-Based Telecom-Emulator (TM, TM), pp. 186–191.
DATE-2000-DonathKSVRSC #synthesis: Transformational Placement and Synthesis (WED, PK, LS, PV, LNR, AS, KC), pp. 194–201.
DATE-2000-KumthekarS #logic #optimisation #reduction: Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs (BK, FS), pp. 202–207.
DATE-2000-KravetsS #symmetry #synthesis #using: Constructive Library-Aware Synthesis Using Symmetries (VNK, KAS), pp. 208–213.
DATE-2000-HuangOC #testing: A BIST Scheme for On-Chip ADC and DAC Testing (JLH, CKO, KTC), pp. 216–220.
DATE-2000-WenL: An on Chip ADC Test Structure (YCW, KJL), pp. 221–225.
DATE-2000-CotaRABCL #reuse #using: Reuse of Existing Resources for Analog BIST of a Switch Capacitor Filte (ÉFC, MR, FA, YB, LC, ML), pp. 226–230.
DATE-2000-KallaZCH #framework #paradigm #recursion #satisfiability #using: A BDD-Based Satisfiability Infrastructure Using the Unate Recursive Paradigm (PK, ZZ, MJC, CH), pp. 232–236.
DATE-2000-YalagandulaAS #automation #generative: Automatic Lighthouse Generation for Directed State Space Search (PY, AA, VS), pp. 237–242.
DATE-2000-RufK #realtime: Analyzing Real-Time Systems (JR, TK), pp. 243–248.
DATE-2000-GuerrierG #architecture: A Generic Architecture for On-Chip Packet-Switched Interconnections (PG, AG), pp. 250–256.
DATE-2000-HarmszeTM #memory management: Memory Arbitration and Cache Management in Stream-Based Systems (FH, AHT, JLvM), pp. 257–262.
DATE-2000-BaleaniFST: HW/SW Codesign of an Engine Management System (MB, AF, ALSV, CT), pp. 263–267.
DATE-2000-MacchiaruloSM: Wave Steered FSMs (LM, SMS, MMS), pp. 270–276.
DATE-2000-CiricYS #implementation #logic #using: Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic (JC, GY, CS), pp. 277–282.
DATE-2000-JacobsB #statistics #using: Gate Sizing Using a Statistical Delay Model (ETAFJ, MRCMB), pp. 283–290.
DATE-2000-CataldoCPW #functional #generative #hardware: Optimal Hardware Pattern Generation for Functional BIST (SC, SC, PP, HJW), pp. 292–297.
DATE-2000-PomeranzR #generative #sequence #testing: Built-In Generation of Weighted Test Sequences for Synchronous Sequential Circuits (IP, SMR), pp. 298–304.
DATE-2000-BergfeldNR #embedded #testing #using: Diagnostic Testing of Embedded Memories Using BIST (TJB, DN, EMR), pp. 305–309.
DATE-2000-SemeriaSM #behaviour #c #memory management #pointer #synthesis: Resolution of Dynamic Memory Allocation and Pointers for the Behavioral Synthesis from C (LS, KS, GDM), pp. 312–319.
DATE-2000-GanesanV00a #clustering #configuration management #design #latency: An Integrated Temporal Partitioning and Partial Reconfiguration Technique for Design Latency Improvement (SG, RV), pp. 320–325.
DATE-2000-BringmannRM #architecture #multi #synthesis: Target Architecture Oriented High-Level Synthesis for Multi-FPGA Based Emulation (OB, WR, CM), pp. 326–332.
DATE-2000-HenkeGV #design #estimation #performance: Fast Cache and Bus Power Estimation for Parameterized System-on-a-Chip Design (JH, TG, FV), pp. 333–338.
DATE-2000-DemirF #evaluation #modelling #performance #probability: Stochastic Modeling and Performance Evaluation for Digital Clock and Data Recovery Circuits (AD, PF), pp. 340–344.
DATE-2000-GouraryRUZGM #approach: A New Approach for Computation of Timing Jitter in Phase Locked Loops (MMG, SGR, SLU, MMZ, KKG, BJM), pp. 345–349.
DATE-2000-WambacqDDEB #communication #modelling: Compact Modeling of Nonlinear Distortion in Analog Communication Circuits (PW, PD, SD, ME, IB), pp. 350–354.
DATE-2000-ManquinhoS #algorithm #on the #satisfiability #using: On Using Satisfiability-Based Pruning Techniques in Covering Algorithms (VMM, JPMS), pp. 356–363.
DATE-2000-CordoneFSC #approach #heuristic #performance #problem: An Efficient Heuristic Approach to Solve the Unate Covering Problem (RC, FF, DS, RWC), pp. 364–371.
DATE-2000-SchollB #generative #logic #multi #on the: On the Generation of Multiplexer Circuits for Pass Transistor Logic (CS, BB), pp. 372–378.
DATE-2000-KimWSS #fault #incremental #on the #satisfiability #testing: On Applying Incremental Satisfiability to Delay Fault Testing (JK, JW, KAS, JPMS), pp. 380–384.
DATE-2000-CornoRSMP #automation #experience #generative #industrial #validation: Automatic Test Bench Generation for Validation of RT-Level Descriptions: An Industrial Experience (FC, MSR, GS, AM, AP), pp. 385–389.
DATE-2000-FinF #fault #functional #generative #testing: A VHDL Error Simulator for Functional Test Generation (AF, FF), pp. 390–395.
DATE-2000-PomeranzR00a #functional #generative #testing: Functional Test Generation for Full Scan Circuits (IP, SMR), pp. 396–401.
DATE-2000-MurthyB #data flow #implementation #memory management #specification: Shared Memory Implementations of Synchronous Dataflow Specifications (PKM, SSB), pp. 404–410.
DATE-2000-Lopez-VallejoGL #clustering #constraints: Constraint-Driven System Partitioning (MLLV, JG, JCL), pp. 411–416.
DATE-2000-ShenoyBC #algorithm #quality #synthesis: A System-Level Synthesis Algorithm with Guaranteed Solution Quality (UNS, PB, ANC), pp. 417–424.
DATE-2000-CatthoorDK #architecture #compilation #data transfer #how #memory management #question: How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? (FC, NDD, CEK), pp. 426–433.
DATE-2000-LiuAW #constraints: Meeting Delay Constraints in DSM by Minimal Repeater Insertion (IML, AA, DFW), pp. 436–440.
DATE-2000-HiroseY #reduction: A Bus Delay Reduction Technique Considering Crosstalk (KH, HY), pp. 441–445.
DATE-2000-AdlerB #multi: Single Step Current Driven Routing of Multiterminal Signal Nets for Analog Applications (TA, EB), pp. 446–450.
DATE-2000-RingeLB #analysis: Static Timing Analysis Taking Crosstalk into Account (MR, TL, EB), pp. 451–455.
DATE-2000-ParkK #bound #design #detection #fault: A New IEEE 1149.1 Boundary Scan Design for the Detection of Delay Defects (SP, TK), pp. 458–462.
DATE-2000-KacNMZ #using: Alternative Test Methods Using IEEE 1149.4 (UK, FN, SM, MSZ), pp. 463–467.
DATE-2000-GoodbyO #fault #quality: Test Quality and Fault Risk in Digital Filter Datapath BIST (LG, AO), pp. 468–475.
DATE-2000-Rosing #fault #simulation: A Fault Simulation Methodology for MEMS (RR), pp. 476–483.
DATE-2000-LogothetisS #abstraction #realtime: Abstraction from Counters: An Application on Real-Time Systems (GL, KS), pp. 486–493.
DATE-2000-Balarin #abstraction #analysis #automation #worst-case: Automatic Abstraction for Worst-Case Analysis of Discrete Systems (FB), pp. 494–501.
DATE-2000-JangMH #model checking: Iterative Abstraction-Based CTL Model Checking (JYJ, IHM, GDH), pp. 502–507.
DATE-2000-GaoW #using: Wire-Sizing for Delay Minimization and Ringing Control Using Transmission Line Model (YG, DFW), pp. 512–516.
DATE-2000-Sheehan #predict: Predicting Coupled Noise in RC Circuits (BNS), pp. 517–521.
DATE-2000-ChangLNXH #modelling #performance: Clocktree RLC Extraction with Efficient Inductance Modeling (NC, SL, OSN, WX, LH), pp. 522–526.
DATE-2000-SuCHCL #metric: All Digital Built-in Delay and Crosstalk Measurement for On-Chip Buses (CS, YTC, MJH, GNC, CLL), pp. 527–531.
DATE-2000-PeraliasARH #design #pipes and filters #verification: A Vhdl-Based Methodology for Design and Verification of Pipeline A/D Converters (EJP, AJA, AR, JLH), pp. 534–538.
DATE-2000-SchefflerT #effectiveness: Assessing the Cost Effectiveness of Integrated Passives (MS, GT), pp. 539–543.
DATE-2000-CarroSNJF #component: Non-Linear Components for Mixed Circuits Analog Front-End (LC, AAdSJ, MN, GPJ, DTF), pp. 544–549.
DATE-2000-HergenhanR #analysis #architecture #embedded: Static Timing Analysis of Embedded Software on Advanced Processor Architectures (AH, WR), pp. 552–559.
DATE-2000-OuaissV #configuration management #performance: Efficient Resource Arbitration in Reconfigurable Computing Environments (IO, RV), pp. 560–566.
DATE-2000-PopEP #analysis #distributed #embedded #optimisation #scheduling: Bus Access Optimization for Distributed Embedded Systems Based on Schedulability Analysis (PP, PE, ZP), pp. 567–574.
DATE-2000-LennardSJHH #design #question #standard: Standards for System-Level Design: Practical Reality or Solution in Search of a Question? (CKL, PS, GGdJ, AH, PH), pp. 576–583.
DATE-2000-LajoloRRVL #co-evolution #dependence #design #framework: Evaluating System Dependability in a Co-Design Framework (ML, MR, MSR, MV, LL), pp. 586–590.
DATE-2000-AnghelN #detection #evaluation #fault #reduction: Cost Reduction and Evaluation of a Temporary Faults Detecting Technique (LA, MN), pp. 591–598.
DATE-2000-WeilerMHH #detection #using: Detection of Defective Sensor Elements Using Sigma-Delta-Modulation and a Matched Filter (DW, OM, DH, BJH), pp. 599–603.
DATE-2000-RamanathanG #algorithm #online #power management: System Level Online Power Management Algorithms (DR, RKG), pp. 606–611.
DATE-2000-HsiehP #architecture #optimisation: Architectural Power Optimization by Bus Splitting (CTH, MP), pp. 612–616.
DATE-2000-IshiharaY #embedded #reduction: A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors (TI, HY), pp. 617–623.
DATE-2000-MunchWWMS #automation #power management: Automating RT-Level Operand Isolation to Minimize Power Consumption in Datapaths (MM, NW, BW, RM, JS), pp. 624–631.
DATE-2000-Nassif #design: Designing Closer to the Edge (SRN), pp. 636–637.
DATE-2000-SousaA #clustering #complexity #fault #modelling #using: Reducing the Complexity of Defect Level Modeling Using the Clustering Effect (JTdS, VDA), pp. 640–644.
DATE-2000-DiezL #metric: Influence of Manufacturing Variations in IDDQ Measurements: A New Test Criterion (JMD, JCL), pp. 645–649.
DATE-2000-SaabHK #fault #generative #parametricity #simulation: Parametric Fault Simulation and Test Vector Generation (KS, NBH, BK), pp. 650–656.
DATE-2000-LungeanuS #distributed #parallel #simulation: Parallel and Distributed VHDL Simulation (DL, CJRS), pp. 658–662.
DATE-2000-YooLJRCC #execution #performance: Fast Hardware-Software Coverification by Optimistic Execution of Real Processor (SY, JeL, JJ, KR, YC, KC), pp. 663–668.
DATE-2000-PeesHM #using: Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language (SP, AH, HM), pp. 669–673.
DATE-2000-Maurer #logic #network #simulation #state machine #using: Logic Simulation Using Networks of State Machines (PMM), pp. 674–678.
DATE-2000-FrohlichGF #clustering #parallel #simulation: A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level (NF, VG, JF), pp. 679–684.
DATE-2000-RustSAT #embedded #implementation #parallel #realtime #specification: From High-Level Specifications Down to Software Implementations of Parallel Embedded Real-Time Systems (CR, FS, PA, JT), pp. 686–691.
DATE-2000-EdwardsG #configuration management #design #object-oriented: An Object Oriented Design Method for Reconfigurable Computing Systems (ME, PG), pp. 692–696.
DATE-2000-CarroKWO #embedded #multi #synthesis: System Synthesis for Multiprocessor Embedded Applications (LC, MEK, FRW, MO), pp. 697–702.
DATE-2000-ItoCJ #design #java: System Design Based on Single Language and Single-Chip Java ASIP Microcontroller (SAI, LC, RPJ), pp. 703–707.
DATE-2000-LuW #logic #memory management #modelling: Cost and Benefit Models for Logic and Memory BIST (JML, CWW), pp. 710–714.
DATE-2000-NicoliciA #clustering #multi #power management: Scan Latch Partitioning into Multiple Scan Chains for Power Minimization in Full Scan Sequential Circuits (NN, BMAH), pp. 715–722.
DATE-2000-CarlettaPN #analysis #detection #fault #using: Detecting Undetectable Controller Faults Using Power Analysis (JC, CAP, MN), pp. 723–728.
DATE-2000-GulrajaniH #identification #logic #multi: Multi-Node Static Logic Implications for Redundancy Identification (KG, MSH), pp. 729–733.
DATE-2000-SimunicBGM #power management: Dynamic Power Management of Laptop Hard Disk (TS, LB, PWG, GDM), p. 736.
DATE-2000-KruseSJSN #bound #constraints #data flow #graph #power management: Lower Bounds on the Power Consumption in Scheduled Data Flow Graphs with Resource Constraints (LK, ES, GJ, AS, WN), p. 737.
DATE-2000-PaulusKT #constraints #optimisation: Area Optimization of Analog Circuits Considering Matching Constraints (CP, UK, RT), p. 738.
DATE-2000-Perez-MontesMDFR #named: XFridge: A SPICE-Based, Portable, User-Friendly Cell-Level Sizing Tool (FMPM, FM, RDC, FVF, ÁRV), p. 739.
DATE-2000-Pillkahn #evaluation: Evaluation of Interconnects with TDR (UP), p. 740.
DATE-2000-BachB #testing: Structural Testing on Real Boards (PB, MB), p. 741.
DATE-2000-GauthierJ #simulation: Cycle-True Simulation of the ST10 Microcontroller (LG, AAJ), p. 742.
DATE-2000-MorawiecUR #algorithm #diagrams #simulation #using: Cycle-Based Simulation Algorithms for Digital Systems Using High-Level Decision Diagrams (AM, RU, JR), p. 743.
DATE-2000-SilvaDM #configuration management #correlation #hardware #using: Mixed-Signal BIST Using Correlation and Reconfigurable Hardware (JMdS, JSD, JSM), p. 744.
DATE-2000-SakallahAS #case study #heuristic #satisfiability: An Experimental Study of Satisfiability Search Heuristics (KAS, FAA, JPMS), p. 745.
DATE-2000-ChangKK #architecture #memory management #video: A Memory Architecture with 4-Address Configurations for Video Signal Processing (SC, JSK, LSK), p. 746.
DATE-2000-HaugKR #design #framework #hardware #platform: A Hardware Platform for VLIW Based Emulation of Digital Designs (GH, UK, WR), p. 747.
DATE-2000-HalambiCGDN #architecture: Architecture Exploration of Parameterizable EPIC SOC Architectures (AH, RC, PG, NDD, AN), p. 748.
DATE-2000-GovindarajanV #quality #scheduling: Improving the Schedule Quality of Static-List Time-Constrained Scheduling (SG, RV), p. 749.
DATE-2000-YangC #logic #synthesis: Synthesis for Mixed CMOS/PTl Logic (CY, MJC), p. 750.
DATE-2000-DubrovaEMM #algorithm #named #optimisation: TOP: An Algorithm for Three-Level Optimization of PLDs (ED, PE, DMM, JCM), p. 751.
DATE-2000-SosnowskiB #testing: Testing Arithmetic Coprocessor in System Environment (JS, TB), p. 752.
DATE-2000-MoyaMLD #flexibility #framework #specification: A Flexible Specification Framework for Hardware-Software Codesign (JMM, FM, JCL, SD), p. 753.
DATE-2000-ZuoD #concept #design: An Integrated Design Environment for Early Stage Conceptual Design (JZ, SWD), p. 754.
DATE-2000-KahnCW #design: A Web-Based System for Assessing and Searching for Designs (HJK, AC, NAW), p. 755.
DATE-2000-TsiatouhasHAN #fault #self #testing: A Versatile Built-In Self-Test Scheme for Delay Fault Testing (YT, TH, AA, DN), p. 756.
DATE-2000-GizopoulosKPPZ #effectiveness #power management: Effective Low Power BIST for Datapaths (DG, NK, MP, AMP, YZ), p. 757.
DATE-2000-HoffmannK #fault #multi: Exploiting Hierarchy for Multiple Error Correction in Combinational Circuits (DWH, TK), p. 758.
DATE-2000-SchonherrS #algorithm #automation #equivalence: Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level (JS, BS), p. 759.
DATE-2000-NooshabadiMNSS: A Single Phase Latch for High Speed GaAs Domino Circuits (SN, JAMN, AN, RS, JS), p. 760.
DATE-2000-NiemegeersJ #embedded #incremental #realtime #specification: An Incremental Specification Flow for Real Time Embedded Systems (AN, GGdJ), p. 761.
DATE-2000-VardanianM #concurrent #detection #fault: Improving the Error Detection Ability of Concurrent Checkers by Observation Point Insertion in the Circuit Under Check (VAV, LBM), p. 762.
DATE-2000-MetraFR #online #testing: On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values (CM, MF, BR), p. 763.
DATE-2000-WegenerK #modelling #testing: Incorporation of Hard-Fault-Coverage in Model-Based Testing of Mixed-Signal ICs (CW, MPK), p. 765.

Proceedings of the Fifth Conference on Design, Automation and Test in EuropeDATE, 2000.

Contents (143 items)

Proceedings of the Fifth Conference on Design, Automation and Test in Europe
DATE, 2000.