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Travelled to:
1 × France
Collaborated with:
W.Verhaegen A.Agarwal H.Sampath R.Vemuri G.G.E.Gielen
Talks about:
synthesi (1) perform (1) parasit (1) circuit (1) symbol (1) layout (1) inclus (1) compil (1) analog (1) model (1)

Person: Mukesh Ranjan

DBLP DBLP: Ranjan:Mukesh

Contributed to:

DATE v1 20042004

Wrote 1 papers:

DATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using
Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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