BibSLEIGH — Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 1

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 1
DATE v1, 2004.

SYS

@proceedings{DATE-v1-2004,
	address       = "Paris, France",
	isbn          = "0-7695-2085-5",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 1}",
	year          = 2004,
}

Contents (143 items)

DATE-v1-2004-Spirakis #challenge: Opportunities and Challenges in Building Silicon Products in 65nm and Beyond (GS), pp. 2–3.
DATE-v1-2004-ChoiSP #energy #fine-grained #performance #precise #scalability #trade-off: Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times (KC, RS, MP), pp. 4–9.
DATE-v1-2004-Skadron #architecture #hybrid: Hybrid Architectural Dynamic Thermal Management (KS), pp. 10–15.
DATE-v1-2004-ChangYL: Value-Conscious Cache: Simple Technique for Reducing Cache Access Power (YJC, CLY, FL), pp. 16–21.
DATE-v1-2004-LiPZSSS: State-Preserving vs. Non-State-Preserving Leakage Control in Caches (YL, DP, YZ, KS, MRS, KS), pp. 22–29.
DATE-v1-2004-WedlerSK #reasoning #satisfiability: Arithmetic Reasoning in DPLL-Based SAT Solving (MW, DS, WK), pp. 30–35.
DATE-v1-2004-BaumgartnerK #bound: Enhanced Diameter Bounding via Structural (JB, AK), pp. 36–41.
DATE-v1-2004-FengWCL #clustering #simulation: Improved Symoblic Simulation by Dynamic Funtional Space Partitioning (TF, LCW, KTC, CCL), pp. 42–49.
DATE-v1-2004-PadmanabanT #fault #identification #performance #using: Using BDDs and ZBDDs for Efficient Identification of Testable Path Delay Faults (SP, ST), pp. 50–55.
DATE-v1-2004-PomeranzR #fault #metric #similarity: Level of Similarity: A Metric for Fault Collapsing (IP, SMR), pp. 56–61.
DATE-v1-2004-BonhommeGGLPV #design #power management: Design of Routing-Constrained Low Power Scan Chains (YB, PG, LG, CL, SP, AV), pp. 62–67.
DATE-v1-2004-PomeranzVRS #detection #fault: Z-Sets and Z-Detections: Circuit Characteristics that Simplify Fault Diagnosis (IP, SV, SMR, BS), pp. 68–75.
DATE-v1-2004-NagariN #algorithm #multi: A 2.7V 350muW 11-b Algorithmic Analog-to-Digital Converter with Single-Ended Multiplexed Inputs (AN, GN), pp. 76–81.
DATE-v1-2004-GinesPR #fault #pipes and filters: Digital Background Gain Error Correction in Pipeline ADCs (AJG, EJP, AR), pp. 82–87.
DATE-v1-2004-BadarogluWPDGM #reduction: Digital Ground Bounce Reduction by Phase Modulation of the Clock (MB, PW, GVdP, SD, GGEG, HDM), pp. 88–93.
DATE-v1-2004-CorsiMMBD #pseudo #sequence: Pseudo-Random Sequence Based Tuning System for Continuous-Time Filters (FC, CM, GM, AB, SD), pp. 94–101.
DATE-v1-2004-LiVKI: A Crosstalk Aware Interconnect with Variable Cycle Transmission (LL, NV, MTK, MJI), pp. 102–107.
DATE-v1-2004-ThepayasuwanD #architecture #layout #synthesis: Layout Conscious Bus Architecture Synthesis for Deep Submicron Systems on Chip (NT, AD), pp. 108–113.
DATE-v1-2004-GuptaDGN #control flow #design #synthesis: Loop Shifting and Compaction for the High-Level Synthesis of Designs with Complex Control Flow (SG, ND, RG, AN), pp. 114–121.
DATE-v1-2004-SciutoMRSGFS #question: SystemC and SystemVerilog: Where do They Fit? Where are They Going? (DS, GM, WR, SS, FG, PF, JS), pp. 122–129.
DATE-v1-2004-WongT #configuration management #encoding #power management: Re-Configurable Bus Encoding Scheme for Reducing Power Consumption of the Cross Coupling Capacitance for Deep Sub-Micron Instruction Bus (SKW, CYT), pp. 130–135.
DATE-v1-2004-RenKM #adaptation #power management: Hierarchical Adaptive Dynamic Power Management (ZR, BHK, RM), pp. 136–141.
DATE-v1-2004-ZhangVL #architecture #embedded #self: A Self-Tuning Cache Architecture for Embedded Systems (CZ, FV, RLL), pp. 142–147.
DATE-v1-2004-HuVKKI #reduction #reuse #scheduling: Scheduling Reusable Instructions for Power Reduction (JSH, NV, SK, MTK, MJI), pp. 148–155.
DATE-v1-2004-BjesseK #abstraction #debugging #refinement #using: Using Counter Example Guided Abstraction Refinement to Find Complex Bugs (PB, JHK), pp. 156–161.
DATE-v1-2004-WinkelmannTSF #low cost #verification: Cost-Efficient Block Verification for a UMTS Up-Link Chip-Rate Coprocessor (KW, HJT, DS, GF), pp. 162–167.
DATE-v1-2004-ManoliosS #automation #liveness #modelling #safety #using #verification #web: Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements (PM, SKS), pp. 168–175.
DATE-v1-2004-FernandesSOT #probability #testing: A Probabilistic Method for the Computation of Testability of RTL Constructs (JMF, MBS, ALO, JPT), pp. 176–181.
DATE-v1-2004-MishraD #functional #generative #graph #pipes and filters: Graph-Based Functional Test Program Generation for Pipelined Processors (PM, ND), pp. 182–187.
DATE-v1-2004-GoloubevaRV #automation #generative #validation: Automatic Generation of Validation Stimuli for Application-Specific Processors (OG, MSR, MV), pp. 188–193.
DATE-v1-2004-DimopoulosL #performance #sequence #set #testing: Efficient Static Compaction of Test Sequence Sets through the Application of Set Covering Techniques (MGD, PL), pp. 194–201.
DATE-v1-2004-IsseninBMD #analysis #memory management #reuse: Data Reuse Analysis Technique for Software-Controlled Memory Hierarchies (II, EB, MM, ND), pp. 202–207.
DATE-v1-2004-Gordon-RossVD #automation #embedded: Automatic Tuning of Two-Level Caches to Embedded Applications (AGR, FV, ND), pp. 208–213.
DATE-v1-2004-ZhangYV: Low Static-Power Frequent-Value Data Caches (CZ, JY, FV), pp. 214–219.
DATE-v1-2004-ZhangV #memory management #using: Using a Victim Buffer in an Application-Specific Memory Hierarchy (CZ, FV), pp. 220–227.
DATE-v1-2004-RenaudinBPTSG #security: High Security Smartcards (MR, GFB, PP, JPT, LS, FG), pp. 228–233.
DATE-v1-2004-HuM #architecture #communication #constraints #energy #realtime #scheduling: Energy-Aware Communication and Task Scheduling for Network-on-Chip Architectures under Real-Time Constraints (JH, RM), pp. 234–239.
DATE-v1-2004-ChenG #adaptation #bias #low cost #performance #power management #reduction: A Low Cost Individual-Well Adaptive Body Bias (IWABB) Scheme for Leakage Power Reduction and Performance Enhancement in the Presence of Intra-Die Variations (TWC, JG), pp. 240–245.
DATE-v1-2004-TiriV #design #implementation #logic: A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation (KT, IV), pp. 246–251.
DATE-v1-2004-ChengHP #concurrent #power management #scalability: Power Minimization in a Backlit TFT-LCD Display by Concurrent Brightness and Contrast Scaling (WCC, YH, MP), pp. 252–259.
DATE-v1-2004-SafarpourVDL #satisfiability: Managing Don’t Cares in Boolean Satisfiability (SS, AGV, RD, JL), pp. 260–265.
DATE-v1-2004-Velev #performance #verification: Exploiting Signal Unobservability for Efficient Translation to CNF in Formal Verification of Microprocessors (MNV), pp. 266–271.
DATE-v1-2004-LiHS #novel #performance #satisfiability: A Novel SAT All-Solutions Solver for Efficient Preimage Computation (BL, MSH, SS), pp. 272–279.
DATE-v1-2004-SrinivasanBCC #metric #performance #using: Efficient Test Strategy for TDMA Power Amplifiers Using Transient Current Measurements: Uses and Benefit (GS, SB, SC, AC), pp. 280–285.
DATE-v1-2004-OngHCW #multi #random: Random Jitter Extraction Technique in a Multi-Gigahertz Signal (CKO, DH, KTC, LCW), pp. 286–291.
DATE-v1-2004-NegreirosCS #low cost #testing: Low Cost Analog Testing of RF Signal Paths (MN, LC, AAS), pp. 292–297.
DATE-v1-2004-VazquezLHRH #parametricity #self: A Method for Parameter Extraction of Analog Sine-Wave Signals for Mixed-Signal Built-In-Self-Test Applications (DV, GL, GH, AR, JLH), pp. 298–305.
DATE-v1-2004-HettiaratchiC #implementation #novel: A Novel Implementation of Tile-Based Address Mapping (SH, PYKC), pp. 306–311.
DATE-v1-2004-WangH #clustering #memory management #multi #power management #scheduling: Power Aware Variable Partitioning and Instruction Scheduling for Multiple Memory Banks (ZW, XSH), pp. 312–317.
DATE-v1-2004-SzymanekCK #architecture #design #energy #memory management #multi: Time-Energy Design Space Exploration for Multi-Layer Memory Architectures (RS, FC, KK), pp. 318–323.
DATE-v1-2004-RamaniAMS #graph #independence #symmetry: Breaking Instance-Independent Symmetries in Exact Graph Coloring (AR, FAA, ILM, KAS), pp. 324–331.
DATE-v1-2004-CatthoorCMGLMSW #design #how #problem #question #scalability: How Can System-Level Design Solve the Interconnect Technology Scaling Problem? (FC, AC, GM, PG, RL, KM, PvdS, RW), pp. 332–339.
DATE-v1-2004-StefanovZTKD #approach #design #network #process #using: System Design Using Kahn Process Networks: The Compaan/Laura Approach (TS, CZ, AT, BK, EFD), pp. 340–345.
DATE-v1-2004-DensmoreRS #architecture #development #framework #platform #refinement: Microarchitecture Development via Metropolis Successive Platform Refinement (DD, SR, ALSV), pp. 346–351.
DATE-v1-2004-ShinKCCKE #architecture #design #performance: Fast Exploration of Parameterized Bus Architecture for Communication-Centric SoC Design (CS, YTK, EYC, KMC, JTK, SKE), pp. 352–357.
DATE-v1-2004-BrunelNFGL #development #named #process: SoftContract: an Assertion-Based Software Development Process that Enables Design-by-Contract (JYB, MDN, AF, PG, LL), pp. 358–363.
DATE-v1-2004-QuinnLBA #configuration management #framework #network #platform: A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors (DQ, BL, GB, EMA), pp. 364–371.
DATE-v1-2004-GrimmHW #refinement: Refinement of Mixed-Signal Systems with Affine Arithmetic (CG, WH, KW), pp. 372–377.
DATE-v1-2004-PosadasHSVB #analysis #performance: System-Level Performance Analysis in SystemC (HP, FH, PS, EV, FB), pp. 378–383.
DATE-v1-2004-MousaviGTSB #design #framework #modelling #validation: Modeling and Validating Globally Asynchronous Design in Synchronous Frameworks (MRM, PLG, JPT, SKS, TB), pp. 384–389.
DATE-v1-2004-DSilvaRS #architecture #automaton #communication #framework #modelling #protocol #verification: Synchronous Protocol Automata: A Framework for Modelling and Verification of SoC Communication Architectures (VD, SR, AS), pp. 390–395.
DATE-v1-2004-SeceleanuW #aspect-oriented #design #visual notation: Aspects of Formal and Graphical Design of a Bus System (TS, TW), pp. 396–403.
DATE-v1-2004-SinanogluO #power management: Scan Power Minimization through Stimulus and Response Transformations (OS, AO), pp. 404–409.
DATE-v1-2004-HeathBH #named #nondeterminism: Synchro-Tokens: Eliminating Nondeterminism to Enable Chip-Level Test of Globally-Asynchronous Locally-Synchronous SoC?s (MWH, WPB, IGH), pp. 410–415.
DATE-v1-2004-XuN #design #multi #testing: Wrapper Design for Testing IP Cores with Multiple Clock Domains (QX, NN), pp. 416–421.
DATE-v1-2004-SehgalC #architecture #composition #performance #testing #using: Efficient Modular Testing of SOCs Using Dual-Speed TAM Architectures (AS, KC), pp. 422–427.
DATE-v1-2004-FlottesPR #testing: An Arithmetic Structure for Test Data Horizontal Compression (MLF, RP, BR), pp. 428–435.
DATE-v1-2004-MartensG #architecture #design: A Phase-Frequency Transfer Description of Analog and Mixed-Signal Front-End Architectures for System-Level Design (EM, GGEG), pp. 436–441.
DATE-v1-2004-NathkeBHB #automation #behaviour #generative: Hierarchical Automatic Behavioral Model Generation of Nonlinear Analog Circuits Based on Nonlinear Symbolic Techniques (LN, VB, LH, EB), pp. 442–447.
DATE-v1-2004-KielyG #modelling #performance #using: Performance Modeling of Analog Integrated Circuits Using Least-Squares Support Vector Machines (TK, GGEG), pp. 448–453.
DATE-v1-2004-VandersteenPLD #identification #linear: Extended Subspace Identification of Improper Linear Systems (GV, RP, DL, SD), pp. 454–459.
DATE-v1-2004-HuangM #behaviour #identification #modelling: Identification and Modeling of Nonlinear Dynamic Behavior in Analog Circuits (XH, HAM), pp. 460–467.
DATE-v1-2004-KoorapatyKGFP #logic: Exploring Logic Block Granularity for Regular Fabrics (AK, VK, PG, MF, LTP), pp. 468–473.
DATE-v1-2004-BansalGDNG #architecture #configuration management #network: Network Topology Exploration of Mesh-Based Coarse-Grain Reconfigurable Architectures (NB, SG, ND, AN, RG), pp. 474–479.
DATE-v1-2004-LyseckyV #architecture #clustering #configuration management #hardware #logic: A Configurable Logic Architecture for Dynamic Hardware/Software Partitioning (RLL, FV), pp. 480–485.
DATE-v1-2004-ChenKS #platform #process #scheduling: Configuration-Sensitive Process Scheduling for FPGA-Based Computing Platforms (GC, MTK, US), pp. 486–493.
DATE-v1-2004-LeeDBS #power management: Simultaneous State, Vt and Tox Assignment for Total Standby Power Minimization (DL, HD, DB, DS), pp. 494–499.
DATE-v1-2004-BabighianBM #algorithm #scalability: A Scalable ODC-Based Algorithm for RTL Insertion of Gated Clocks (PB, LB, EM), pp. 500–505.
DATE-v1-2004-Kandemir #data transformation #locality #memory management: Impact of Data Transformations on Memory Bank Locality (MTK), pp. 506–511.
DATE-v1-2004-KretzschmarNM #power management #why: Why Transition Coding for Power Minimization of On-Chip Buses Does Not Work (CK, AKN, DM), pp. 512–517.
DATE-v1-2004-AndreiSEPA #energy #reduction: Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems (AA, MTS, PE, ZP, BMAH), pp. 518–525.
DATE-v1-2004-CaiL #power management #using: Dynamic Power Management Using Data Buffers (LC, YHL), pp. 526–531.
DATE-v1-2004-AtienzaMCMS #design #memory management #multi #network: Dynamic Memory Management Design Methodology for Reduced Memory Footprint in Multimedia and Wireless Network Applications (DA, SM, FC, JMM, DS), pp. 532–537.
DATE-v1-2004-JangKLCLS #architecture #case study #modelling #network: High-Level System Modeling and Architecture Exploration with SystemC on a Network SoC: S3C2510 Case Study (HOJ, MK, MjL, KC, KL, KS), pp. 538–543.
DATE-v1-2004-PostVRS #verification: A SystemC-Based Verification Methodology for Complex Wireless Software IP (GP, PKV, TR, DRS), pp. 544–551.
DATE-v1-2004-PerezMT #scheduling #using: A New Optimized Implemention of the SystemC Engine Using Acyclic Scheduling (DGP, GM, OT), pp. 552–557.
DATE-v1-2004-Ziv #generative: Stimuli Generation with Late Binding of Values (AZ), pp. 558–563.
DATE-v1-2004-FummiMPP #integration #multi: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC (FF, SM, GP, MP), pp. 564–569.
DATE-v1-2004-BoseN #array #memory management #modelling: Extraction of Schematic Array Models for Memory Circuits (SB, AN), pp. 570–577.
DATE-v1-2004-PaschalisG #effectiveness #embedded #online #self #testing: Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors (AMP, DG), pp. 578–583.
DATE-v1-2004-BellatoBBCCPRRVZ #memory management: Evaluating the Effects of SEUs Affecting the Configuration Memory of an SRAM-Based FPGA (MB, PB, DB, AC, MC, AP, MR, MSR, MV, PZ), pp. 584–589.
DATE-v1-2004-LeveugleA #fault #injection: Early SEU Fault Injection in Digital, Analog and Mixed Signal Circuits: A Global Flow (RL, AA), pp. 590–595.
DATE-v1-2004-AlmukhaizimDM #bound #concurrent #detection #fault #latency #on the: On Concurrent Error Detection with Bounded Latency in FSMs (SA, PD, YM), pp. 596–603.
DATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using: Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.
DATE-v1-2004-MurgaiRMHT #analysis #modelling: Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis (RM, SMR, TM, TH, MBT), pp. 610–615.
DATE-v1-2004-BrandtnerW #named #simulation: SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level (TB, RW), pp. 616–621.
DATE-v1-2004-ZhanS #optimisation #polynomial #programming #using: Optimization of Integrated Spiral Inductors Using Sequential Quadratic Programming (YZ, SSS), pp. 622–629.
DATE-v1-2004-DebJO #design #using: System Design for DSP Applications Using the MASIC Methodology (AKD, AJ, JÖ), pp. 630–635.
DATE-v1-2004-ZambrenoCSN #flexibility #hardware #using: Flexible Software Protection Using Hardware/Software Codesign Techniques (JZ, ANC, RS, BN), pp. 636–641.
DATE-v1-2004-SchaumontV #interactive #partial evaluation: Interactive Cosimulation with Partial Evaluation (PS, IV), pp. 642–647.
DATE-v1-2004-SiebenbornBR #analysis #communication #design: Communication Analysis for System-On-Chip Design (AS, OB, WR), pp. 648–655.
DATE-v1-2004-PiguetGHOS #logic #power management: Extremely Low-Power Logic (CP, JG, CH, IO, US), pp. 656–663.
DATE-v1-2004-KuoHW #composition #design #power management: Decomposition of Instruction Decoder for Low Power Design (WAK, TH, ACHW), pp. 664–665.
DATE-v1-2004-LaurentJSM #analysis #approach #functional #modelling #performance #power management: Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors (JL, NJ, ES, EM), pp. 666–667.
DATE-v1-2004-BasuDDCMF #architecture #design #question #verification: Formal Verification Coverage: Are the RTL-Properties Covering the Design’s Architectural Intent? (PB, SD, PD, PPC, CRM, LF), pp. 668–669.
DATE-v1-2004-KwonK #functional #generative #graph #metric: Functional Coverage Metric Generation from Temporal Event Relation Graph (YSK, CMK), pp. 670–671.
DATE-v1-2004-EfthymiouSE #automation #generative: Automatic Scan Insertion and Pattern Generation for Asynchronous Circuits (AE, CPS, DAE), pp. 672–673.
DATE-v1-2004-AboushadyLBL #automation #simulation #synthesis: Automatic Synthesis and Simulation of Continuous-Time [Sigma-Delta] Modulators (HA, LdL, NB, MML), pp. 674–675.
DATE-v1-2004-BernardinisS #design: A Methodology for System-Level Analog Design Space Exploration (FDB, ALSV), pp. 676–677.
DATE-v1-2004-Taherzadeh-SaniLS #design #optimisation #pipes and filters: Systematic Design for Optimization of High-Resolution Pipelined ADCs (MTS, RL, OS), pp. 678–679.
DATE-v1-2004-GarciaMSN #scalability: A Direct Bootstrapped CMOS Large Capacitive-Load Driver Circuit (JCG, JAMN, JS, HN), pp. 680–681.
DATE-v1-2004-HounsellT #embedded #synthesis: Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration (BIH, RT), pp. 682–683.
DATE-v1-2004-MolinaRMH #behaviour #scheduling: Behavioural Bitwise Scheduling Based on Computational Effort Balancing (MCM, RRS, JMM, RH), pp. 684–685.
DATE-v1-2004-ReNR #automation #generative: A Tool for Automatic Generation of RTL-Level VHDL Description of RNS FIR Filters (ADR, AN, MR), pp. 686–687.
DATE-v1-2004-Cao #on the #power management: On Transfer Function and Power Consumption Transient Response (LC), pp. 688–689.
DATE-v1-2004-RaudvereSSJ #abstraction #polynomial #verification: Polynomial Abstraction for Verification of Sequentially Implemented Combinational Circuits (TR, AKS, IS, AJ), pp. 690–691.
DATE-v1-2004-Wang #learning #simulation #validation: Regression Simulation: Applying Path-Based Learning In Delay Test and Post-Silicon Validation (LCW), pp. 692–695.
DATE-v1-2004-IranliCP #approach #energy #game studies #streaming #video: A Game Theoretic Approach to Low Energy Wireless Video Streaming (AI, KC, MP), pp. 696–697.
DATE-v1-2004-BeniniIMM #design #memory management #metaprogramming: Block-Enabled Memory Macros: Design Space Exploration and Application-Specific Tuning (LB, AI, AM, EM), pp. 698–699.
DATE-v1-2004-PatelMP #architecture #energy #memory management #multi #synthesis: Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC (KP, EM, MP), pp. 700–701.
DATE-v1-2004-NikitovicB #mobile #power management: A Low Power Strategy for Future Mobile Terminals (MN, MB), pp. 702–703.
DATE-v1-2004-BhuniaRR #analysis #using: Trim Bit Setting of Analog Filters Using Wavelet-Based Supply Current Analysis (SB, AR, KR), pp. 704–705.
DATE-v1-2004-RolindezMPB #generative #implementation: A 0.18 µm CMOS Implementation of On-chip Analogue Test Signal Generation from Digital Test Patterns (LR, SM, GP, AB), pp. 706–707.
DATE-v1-2004-LegerR #first-order: A Digital Test for First-Order [Sigma-Delta] Modulators (GL, AR), pp. 708–709.
DATE-v1-2004-ChinN #scheduling #trade-off: SoC Test Scheduling with Power-Time Tradeoff and Hot Spot Avoidance (JC, MN), pp. 710–711.
DATE-v1-2004-BenabdenbiGPVT #named #testing: STEPS: Experimenting a New Software-Based Strategy for Testing SoCs Containing P1500-Compliant IP Cores (MB, AG, FP, EV, MT), pp. 712–713.
DATE-v1-2004-MetraMO #design #fault #question #testing: Are Our Design for Testability Features Fault Secure? (CM, TMM, MO), pp. 714–715.
DATE-v1-2004-WolffPM #hardware: Test Compression and Hardware Decompression for Scan-Based SoCs (FGW, CAP, DRM), pp. 716–717.
DATE-v1-2004-SrivastavaSB #concurrent #design #power management: Concurrent Sizing, Vdd and Vth Assignment for Low-Power Design (AS, DS, DB), pp. 718–719.
DATE-v1-2004-BabighianBM04a #distributed: Sizing and Characterization of Leakage-Control Cells for Layout-Aware Distributed Power-Gating (PB, LB, EM), pp. 720–723.
DATE-v1-2004-BurnsSKY #synthesis #tool support #using: An Asynchronous Synthesis Toolset Using Verilog (FPB, DS, AK, AY), pp. 724–725.
DATE-v1-2004-Dittmann #library: Organizing Libraries of DFG Patterns (GD), pp. 726–727.
DATE-v1-2004-MolnosHCE #composition #data-driven #memory management: Compositional Memory Systems for Data Intensive Applications (AMM, MJMH, SC, JTJvE), pp. 728–729.
DATE-v1-2004-AlakarhuN #estimation #locality #metric #performance: Scalar Metric for Temporal Locality and Estimation of Cache Performance (JA, JN), pp. 730–731.
DATE-v1-2004-LapalmeANCBDB #dot-net #framework #generative #modelling #simulation #tool support: .NET Framework — A Solution for the Next Generation Tools for System-Level Modeling and Simulation (JL, EMA, GN, LC, FRB, JPD, GB), pp. 732–733.
DATE-v1-2004-VianaBRAA #design #memory management #modelling #platform #simulation: Modeling and Simulating Memory Hierarchies in a Platform-Based Design Methodology (PV, EB, SR, RA, GA), pp. 734–735.
DATE-v1-2004-GreenE #data flow #uml: Integrating the Synchronous Dataflow Model with UML (PG, SE), pp. 736–737.
DATE-v1-2004-BriereCMMOG #behaviour #design #modelling #tool support: Design and Behavioral Modeling Tools for Optical Network-on-Chip (MB, LC, TM, FM, IO, FG), pp. 738–739.
DATE-v1-2004-TanQL #modelling #scalability #simulation: Hierarchical Modeling and Simulation of Large Analog Circuits (SXDT, ZQ, HL), pp. 740–741.
DATE-v1-2004-WilsonRBKB #behaviour #modelling #performance: Efficient Mixed-Domain Behavioural Modeling of Ferromagnetic Hysteresis Implemented in VHDL-AMS (PRW, JNR, ADB, TJK, JB), pp. 742–743.
DATE-v1-2004-HandaV #algorithm #performance: A Fast Algorithm for Finding Maximal Empty Rectangles for Dynamic FPGA Placement (MH, RV), pp. 744–745.
DATE-v1-2004-Fit-FloreaHK #reliability: Enhancing Reliability of Operational Interconnections in FPGAs (AFF, MH, FK), pp. 746–747.
DATE-v1-2004-VuleticRPI #configuration management #interface #operating system: Operating System Support for Interface Virtualisation of Reconfigurable Coprocessors (MV, LR, LP, PI), p. 748.

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 1DATE v1, 2004.

Contents (143 items)

Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 1
DATE v1, 2004.