Stem parasit$ (all stems)

38 papers:

DATE-2015-LourencoMH #using

Layout-aware sizing of analog ICs using floorplan & routing estimates for parasitic extraction (NCL, RM, NH), pp. 1156–1161.

SAC-2015-MinV #anti #design #evaluation #implementation #novel

Design, implementation and evaluation of a novel anti-virus parasitic malware (BM, VV), pp. 2127–2133.

DAC-2014-LinHL

Parasitic-aware Sizing and Detailed Routing for Binary-weighted Capacitors in Charge-scaling DAC (MPHL, VWHH, CYL), p. 6.

DATE-2013-WangXZWYWNW #using

Active power-gating-induced power/ground noise alleviation using parasitic capacitance of on-chip memories (XW, JX, WZ, XW, YY, ZW, MN, ZW), pp. 1221–1224.

DATE-2011-PasettiCTSDSF

Characterization of an Intelligent Power Switch for LED driving with control of wiring parasitics effects (GP, NC, FT, RS, PD, SS, LF), pp. 1119–1120.

HCI-AUII-2009-IizukaAM #behaviour #using

The Anticipation of Human Behavior Using “Parasitic Humanoid” (HI, HA, TM), pp. 284–293.

DAC-2008-KshirsagarEB #analysis #performance

Analysis and implications of parasitic and screening effects on the high-frequency/RF performance of tunneling-carbon nanotube FETs (CK, MNEZ, KB), pp. 250–255.

DAC-2006-YangCGJ #algorithm #matrix #parallel #rank #scalability

A parallel low-rank multilevel matrix compression algorithm for parasitic extraction of electrically large structures (CY, SC, DG, VJ), pp. 1053–1056.

DAC-2005-BhattacharyaJS #optimisation

Template-driven parasitic-aware optimization of analog integrated circuit layouts (SB, NJ, CJRS), pp. 644–647.

DAC-2005-GopeCJ #3d #multi #named #performance

DiMES: multilevel fast direct solver based on multipole expansions for parasitic extraction of massively coupled 3D microelectronic structures (DG, IC, VJ), pp. 159–162.

DAC-2005-XuGFM

A green function-based parasitic extraction method for inhomogeneous substrate layers (CX, RG, TSF, KM), pp. 141–146.

DATE-2005-LiS #performance #simulation

An Efficiently Preconditioned GMRES Method for Fast Parasitic-Sensitive Deep-Submicron VLSI Circuit Simulation (ZL, CJRS), pp. 752–757.

DAC-2004-AgarwalSYV #modelling #performance

Fast and accurate parasitic capacitance models for layout-aware (AA, HS, VY, RV), pp. 145–150.

DAC-2004-GopeCJ #matrix #modelling #multi #performance #rank

A fast parasitic extractor based on low-rank multilevel matrix compression for conductor and dielectric modeling in microelectronics and MEMS (DG, SC, VJ), pp. 794–799.

DAC-2004-SilveiraP #algorithm #network #reduction

Exploiting input information in a model reduction algorithm for massively coupled parasitic networks (LMS, JRP), pp. 385–388.

DAC-2004-ZhangDRRC #performance #synthesis #towards

A synthesis flow toward fast parasitic closure for radio-frequency integrated circuits (GZ, EAD, RAR, RAR, LRC), pp. 155–158.

DATE-DF-2004-DaglioIRRS #component #performance #simulation

Building the Hierarchy from a Flat Netlist for a Fast and Accurate Post-Layout Simulation with Parasitic Components (PD, DI, DR, CR, SS), pp. 336–337.

DATE-v1-2004-RanjanVASVG #modelling #performance #synthesis #using

Fast, Layout-Inclusive Analog Circuit Synthesis using Pre-Compiled Parasitic-Aware Symbolic Performance Models (MR, WV, AA, HS, RV, GGEG), pp. 604–609.

DATE-v2-2004-AgarwalSYV #estimation

Accurate Estimation of Parasitic Capacitances in Analog Circuits (AA, HS, VY, RV), pp. 1364–1365.

DAC-2003-QinC #reduction #using

Realizable parasitic reduction using generalized Y-Delta transformation (ZQ, CKC), pp. 220–225.

DATE-2002-CathelinSBLC

Substrate Parasitic Extraction for RF Integrated Circuits (AC, DS, DB, YL, FC), p. 1107.

DATE-2002-ThielenV #performance #simulation

Fast Method to Include Parasitic Coupling in Circuit Simulations (BLAVT, GAEV), pp. 1033–1037.

DAC-2001-KarandikarS #logic

Technology Mapping for SOI Domino Logic Incorporating Solutions for the Parasitic Bipolar Effect (SKK, SSS), pp. 377–382.

DAC-2000-LevySMW #analysis #performance

A rank-one update method for efficient processing of interconnect parasitics in timing analysis (HL, WS, DM, JW), pp. 75–78.

DAC-2000-YouVMX #approach #design #multi

A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits (EY, LV, JM, WX), pp. 69–74.

DAC-1999-FranzonBFMPSW #how #question

Parasitic Extraction Accuracy — How Much is Enough? (PDF, MB, AF, SM, RP, RCS, MW), p. 429.

DATE-1999-FeldmanKL #modelling #performance

Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics (PF, SK, DEL), pp. 418–417.

DATE-1999-YeCFCNC #design #verification

Chip-Level Verification for Parasitic Coupling Effects in Deep-Submicron Digital Designs (LY, FCC, PF, RC, NN, FC), pp. 658–663.

DATE-1998-MarquesKWS #3d #algorithm #modelling #order #performance #reduction

An Efficient Algorithm for Fast Parasitic Extraction and Passive Order Reduction of 3D Interconnect Models (NAM, MK, JW, LMS), pp. 538–543.

DAC-1997-Dai #verification

Chip Parasitic Extraction and Signal Integrity Verification (Extended Abstract) (WWMD), pp. 717–719.

OOPSLA-1997-BoylandC #implementation #java #multi

Parasitic Methods: An Implementation of Multi-Methods for Java (JB, GC), pp. 66–76.

ICRE-1996-Hill #requirements

Parasitic Languages for Requirements (MH), pp. 69–75.

DAC-1993-LiuCS #behaviour #simulation #using #verification

Analog System Verification in the Presence of Parasitics Using Behavioral Simulation (EWYL, HCC, ALSV), pp. 159–163.

DAC-1991-Hwang #analysis #named

REX — A VLSI Parasitic Extraction Tool for Electromigration and Signal Analysis (JPH), pp. 717–722.

DAC-1989-WeninVCLG #layout #rule-based #verification

Rule-based VLSI Verification System Constrained by Layout Parasitics (JW, JV, MVC, JL, PG), pp. 662–667.

DAC-1987-SuRT #named

HPEX: A Hierarchical Parasitic Circuit Extractor (SLS, VBR, TNT), pp. 566–569.

DAC-1983-BastianEFHM #simulation #specification

Symbolic Parasitic Extractor for Circuit Simulation (SPECS) (JDB, ME, PJF, CEH, LPM), pp. 346–352.

DAC-1983-TarolliH

Hierarchical circuit extraction with detailed parasitic capacitance (GMT, WJH), pp. 337–345.