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Travelled to:
1 × France
Collaborated with:
T.Brennan N.Rosner A.Aydin T.Bultan P.Subramanyan K.Pasricha D.Reisman A.Susnea S.Malik Georgios Tzimpragos Dilip Vasudevan G.Michelogiannakis Advait Madhavan Jennifer Volk J.Shalf T.Sherwood
Talks about:
analysi (2) superconduct (1) constraint (1) parameter (1) function (1) quantit (1) program (1) circuit (1) acceler (1) tempor (1)

Person: Nestan Tsiskaridze

DBLP DBLP: Tsiskaridze:Nestan

Contributed to:

DATE 20132013
ESEC/FSE 20172017
ASPLOS 20202020

Wrote 3 papers:

DATE-2013-SubramanyanTPRSM #analysis #functional #reverse engineering #using
Reverse engineering digital circuits using functional analysis (PS, NT, KP, DR, AS, SM), pp. 1277–1280.
ESEC-FSE-2017-BrennanTRAB #constraints #normalisation #program analysis
Constraint normalization and parameterized caching for quantitative program analysis (TB, NT, NR, AA, TB), pp. 535–546.
ASPLOS-2020-TzimpragosVTMMV #logic
A Computational Temporal Logic for Superconducting Accelerators (GT, DV, NT, GM, AM, JV, JS, TS), pp. 435–448.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.