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Travelled to:
1 × France
16 × USA
Collaborated with:
R.Kastner Y.Meng B.Agrawal B.Calder S.Mysore M.Tiwari J.Oberg F.T.Chong R.Dixon Ö.Egecioglu S.Sair B.Mazloom B.Hardekopf Joseph McMahan W.Hu A.Irturk N.Srivastava S.Lin K.Banerjee P.Nagpurkar C.Krintz Georgios Tzimpragos Advait Madhavan Dilip Vasudevan X.Li V.Kashyap S.Meiklejohn E.Perelman G.Hamerly Deeksha Dangwal Weilong Cui Xin-Chuan Wu Y.Li N.Shrivastava S.Suri S.Narayanasamy G.Varghese D.B.Strukov H.M.G.Wassel G.L.Loi A.P.Brown R.A.Iltis H.Lee M.Christensen L.Nichols J.Roesch Sung-Yee Guo N.Tsiskaridze G.Michelogiannakis Jennifer Volk J.Shalf J.K.Oberg V.R.Rajarathinam X.Hu Ling Liang S.Li Lei Deng 0003 Pengfei Zuo Yu Ji 0002 Xinfeng Xie Y.Ding C.Liu Y.Xie
Talks about:
analysi (5) flow (5) languag (4) hardwar (4) inform (4) behavior (3) profil (3) architectur (2) framework (2) theoret (2)

Person: Timothy Sherwood

DBLP DBLP: Sherwood:Timothy

Contributed to:

ASPLOS 20142014
DATE 20132013
DAC 20112011
PLDI 20112011
DAC 20102010
ASPLOS 20092009
ASPLOS 20082008
CIAA 20082008
CIAA 20082009
ASPLOS 20062006
CGO 20062006
DAC 20062006
CGO 20052005
DAC 20052005
HPCA 20052005
HPCA 20032003
ASPLOS 20022002
HPCA 20022002
ASPLOS 20172017
ASPLOS 20192019
ASPLOS 20202020

Wrote 25 papers:

ASPLOS-2014-0001KOTRKSHC #named #policy #security
Sapper: a language for hardware-level security policy enforcement (XL, VK, JKO, MT, VRR, RK, TS, BH, FTC), pp. 97–112.
DATE-2013-ObergMSK #framework #hardware #testing
A practical testing framework for isolating hardware timing channels (JO, SM, TS, RK), pp. 1281–1284.
DAC-2011-ObergHITSK #data flow
Information flow isolation in I2C and USB (JO, WH, AI, MT, TS, RK), pp. 254–259.
PLDI-2011-LiTOKCSH #data flow #hardware #named
Caisson: a hardware description language for secure information flow (XL, MT, JO, VK, FTC, TS, BH), pp. 109–120.
DAC-2010-ObergHITSK #analysis #data flow
Theoretical analysis of gate level information flow tracking (JO, WH, AI, MT, TS, RK), pp. 244–247.
ASPLOS-2009-TiwariWMMCS #data flow
Complete information flow tracking from the gates up (MT, HMGW, BM, SM, FTC, TS), pp. 109–120.
ASPLOS-2008-MysoreMAS #comprehension #data flow #visualisation
Understanding and visualizing full systems with data flow tomography (SM, BM, BA, TS), pp. 211–221.
CIAA-2008-DixonES #analysis
Automata-Theoretic Analysis of Bit-Split Languages for Packet Scanning (RD, ÖE, TS), pp. 141–150.
CIAA-J-2008-DixonES09 #analysis
Analysis of Bit-Split Languages for Packet Scanning and Experiments with Wildcard Matching (RD, ÖE, TS), pp. 597–612.
ASPLOS-2006-MysoreASLBS #3d
Introspective 3D chips (SM, BA, NS, SCL, KB, TS), pp. 264–273.
CGO-2006-MysoreASSS #adaptation #profiling
Profiling over Adaptive Ranges (SM, BA, TS, NS, SS), pp. 147–158.
DAC-2006-LoiASLSB #3d #analysis #performance
A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy (GLL, BA, NS, SCL, TS, KB), pp. 991–996.
DAC-2006-MengSK #embedded #power management #reduction
Leakage power reduction of embedded memories on FPGAs through location assignment (YM, TS, RK), pp. 612–617.
CGO-2005-NagpurkarKS #profiling
Phase-Aware Remote Profiling (PN, CK, TS), pp. 191–202.
DAC-2005-MengBISLK #algorithm #design #estimation #performance
MP core: algorithm and design techniques for efficient channel estimation in wireless applications (YM, APB, RAI, TS, HL, RK), pp. 297–302.
HPCA-2005-MengSK #on the #power management #reduction
On the Limits of Leakage Power Reduction in Caches (YM, TS, RK), pp. 154–165.
Catching Accurate Profiles in Hardwar (SN, TS, SS, BC, GV), pp. 269–280.
ASPLOS-2002-SherwoodPHC #automation #behaviour #scalability
Automatically characterizing large scale program behavior (TS, EP, GH, BC), pp. 45–57.
HPCA-2002-SairSC #behaviour
Quantifying Load Stream Behavior (SS, TS, BC), pp. 197–208.
ASPLOS-2017-McMahanCNRGHS #analysis #architecture #composition
An Architecture Supporting Formal and Compositional Binary Analysis (JM, MC, LN, JR, SYG, BH, TS), pp. 177–191.
ASPLOS-2019-DangwalCMS #behaviour
Safer Program Behavior Sharing Through Trace Wringing (DD, WC, JM, TS), pp. 1059–1072.
ASPLOS-2019-TzimpragosMVSS #classification #energy
Boosted Race Trees for Low Energy Classification (GT, AM, DV, DBS, TS), pp. 215–228.
ASPLOS-2019-WuSCL #pointer #using
Protecting Page Tables from RowHammer Attacks using Monotonic Pointers in DRAM True-Cells (XCW, TS, FTC, YL), pp. 645–657.
ASPLOS-2020-HuLL0Z0XDLSX #architecture #framework #learning #named
DeepSniffer: A DNN Model Extraction Framework Based on Learning Architectural Hints (XH, LL, SL, LD0, PZ, YJ0, XX, YD, CL, TS, YX), pp. 385–399.
ASPLOS-2020-TzimpragosVTMMV #logic
A Computational Temporal Logic for Superconducting Accelerators (GT, DV, NT, GM, AM, JV, JS, TS), pp. 435–448.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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