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Travelled to:
1 × USA
Collaborated with:
H.Y.Chang R.C.Dorr
Talks about:
processor (1) analysi (1) switch (1) simul (1) logic (1) fault (1) check (1) self (1)

Person: R. A. Elliott

DBLP DBLP: Elliott:R=_A=

Contributed to:

DAC 19721972

Wrote 1 papers:

DAC-1972-ChangDE #analysis #fault #logic #self #simulation
Logic simulation and fault analysis of a self-checking switching processor (HYC, RCD, RAE), pp. 128–137.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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