BibSLEIGH — processor stem

Used together with:

embed (117)
multi (97)
design (92)
system (92)
base (91)

Stem processor$ (all stems)

845 papers:

DAC-2015-ChungRPG #energy #memory management: Domain wall memory based digital signal processors for area and energy-efficiency (JC, KR, JP, SG), p. 6.
DAC-2015-FernandezJAQVC15a #manycore #off the shelf #resource management: Resource usage templates and signatures for COTS multicore processors (GF, JJ, JA, EQ, TV, FJC), p. 6.
DAC-2015-LeeHLP #data flow #debugging #information management #interface #performance: Efficient dynamic information flow tracking on a processor with core debug interface (JL, IH, YL, YP), p. 6.
DAC-2015-LiuLLWLMLCJ0SY #energy: Ambient energy harvesting nonvolatile processors: from circuit to system (YL, ZL, HL, YW, XL, KM, SL, MFC, SJ, YX, JS, HY), p. 6.
DAC-2015-LiZHLHX #automation #compilation #performance #stack: Compiler directed automatic stack trimming for efficient non-volatile processors (QL, MZ, JH, YL, YH, CJX), p. 6.
DAC-2015-XieZPHLX #energy: Fixing the broken time machine: consistency-aware checkpointing for energy harvesting powered non-volatile processor (MX, MZ, CP, JH, YL, CJX), p. 6.
DATE-2015-DubenSPYAEPP #big data #case study #energy #performance: Opportunities for energy efficient computing: a study of inexact general purpose processors for high-performance and big-data applications (PDD, JS, P, SY, JA, CCE, KVP, TNP), pp. 764–769.
DATE-2015-FuZLX #manycore #memory management: Maximizing common idle time on multi-core processors with shared memory (CF, YZ, ML, CJX), pp. 900–903.
DATE-2015-GheolbanoiuPC #adaptation #hybrid: Hybrid adaptive clock management for FPGA processor acceleration (AG, LP, SC), pp. 1359–1364.
DATE-2015-GomezPBRBFG #design #energy: Reducing energy consumption in microcontroller-based platforms with low design margin co-processors (AG, CP, AB, DR, LB, HF, JPdG), pp. 269–272.
DATE-2015-HuangKGT #scheduling: Run and be safe: mixed-criticality scheduling with temporary processor speedup (PH, PK, GG, LT), pp. 1329–1334.
DATE-2015-KimKKC #manycore #mobile #named: M-DTM: migration-based dynamic thermal management for heterogeneous mobile multi-core processors (YGK, MK, JMK, SWC), pp. 1533–1538.
DATE-2015-KyrtatasSP #algebra #compilation #embedded #linear: A basic linear algebra compiler for embedded processors (NK, DGS, MP), pp. 1054–1059.
DATE-2015-LiaoWC #3d #manycore #online: An online thermal-constrained task scheduler for 3D multi-core processors (CHL, CHPW, KC), pp. 351–356.
DATE-2015-MunchPHH #embedded #manycore #named #realtime #scalability #using: MPIOV: scaling hardware-based I/O virtualization for mixed-criticality embedded real-time systems using non transparent bridges to (multi-core) multi-processor systems (DM, MP, OH, AH), pp. 579–584.
DATE-2015-SedighiPHNN: A CNN-inspired mixed signal processor based on tunnel transistors (BS, IP, XSH, JN, MTN), pp. 1150–1155.
DATE-2015-ZhuCPP #manycore #named: TAPP: temperature-aware application mapping for NoC-based many-core processors (DZ, LC, TMP, MP), pp. 1241–1244.
VLDB-2015-JhaHLCH #approach #in memory #memory management: Improving Main Memory Hash Joins on Intel Xeon Phi Processors: An Experimental Approach (SJ, BH, ML, XC, HPH), pp. 642–653.
SAC-2015-ZiccardiSV #operating system: A time-composable operating system for the Patmos processor (MZ, MS, TV), pp. 1892–1897.
ASPLOS-2015-HicksSKS #debugging #lightweight #named #runtime #specification: SPECS: A Lightweight Runtime Mechanism for Protecting Software from Security-Critical Processor Bugs (MH, CS, STK, JMS), pp. 517–529.
CGO-2015-ZhengLHWJ #approach #debugging #manycore #on the #performance: On performance debugging of unnecessary lock contentions on multicore processors: a replay-based approach (LZ, XL, BH, SW, HJ), pp. 56–67.
HPCA-2015-LiRJOEBFR #throughput: Priority-based cache allocation in throughput processors (DL, MR, DRJ, MO, ME, DB, DSF, SWR), pp. 89–100.
HPCA-2015-MaZLSLLS0N #architecture #energy: Architecture exploration for ambient energy harvesting nonvolatile processors (KM, YZ, SL, KS, XL, YL, JS, YX, VN), pp. 526–537.
HPCA-2015-OzsoyDGAP #detection #framework #online #performance: Malware-aware processors: A framework for efficient online malware detection (MO, CD, IG, NBAG, DVP), pp. 651–661.
HPCA-2015-WangPBAK #alloy #architecture #memory management #named: Alloy: Parallel-serial memory channel architecture for single-chip heterogeneous processor systems (HW, CJP, GB, JHA, NSK), pp. 296–308.
HPCA-2015-ZhaoY #analysis #distance #manycore #reuse #scalability: Studying the impact of multicore processor scaling on directory techniques via reuse distance analysis (MZ, DY), pp. 590–602.
DAC-2014-Chandra #embedded #monitoring #multi #perspective #reliability: Monitoring Reliability in Embedded Processors — A Multi-layer View (VC), p. 6.
DAC-2014-HuWTT #hardware #monitoring #network #security: System-Level Security for Network Processors with Hardware Monitors (KH, TW, TT, RT), p. 6.
DAC-2014-KoestersG #verification: Verification of Non-Mainline Functions in Todays Processor Chips (JK, AG), p. 3.
DAC-2014-KongKPSW #embedded #framework #named #novel: PUFatt: Embedded Platform Attestation Based on Novel Processor-Based PUFs (JK, FK, PKP, ARS, CW), p. 6.
DAC-2014-KriebelRSSH #adaptation #fault #named: ASER: Adaptive Soft Error Resilience for Reliability-Heterogeneous Processors in the Dark Silicon Era (FK, SR, DS, MS, JH), p. 6.
DAC-2014-NahirDKRRSSW #validation: Post-Silicon Validation of the IBM POWER8 Processor (AN, MD, SK, KR, WR, KDS, KS, GW), p. 6.
DAC-2014-RaiHST #detection #fault #framework #performance #realtime: An Efficient Real Time Fault Detection and Tolerance Framework Validated on the Intel SCC Processor (DR, PH, NS, LT), p. 6.
DATE-2014-BortolottiBWRB #architecture #hybrid #manycore #memory management #power management #scalability: Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors (DB, AB, CW, DR, LB), pp. 1–6.
DATE-2014-BournoutianO #framework #mobile #optimisation: On-device objective-C application optimization framework for high-performance mobile processors (GB, AO), pp. 1–6.
DATE-2014-CaplanMMM #execution #reliability #trade-off: Trade-offs in execution signature compression for reliable processor systems (JC, MIM, PM, BHM), pp. 1–6.
DATE-2014-DinechinAPL #parallel: Time-critical computing on a single-chip massively parallel processor (BDdD, DvA, MP, GL), pp. 1–6.
DATE-2014-EbrahimiETSCA #analysis #embedded #fault: Comprehensive analysis of alpha and neutron particle-induced soft errors in an embedded processor at nanoscales (ME, AE, MBT, RS, EC, DA), pp. 1–6.
DATE-2014-Fu0PJZ #data flow #detection #fault #parallel #thread: A fault detection mechanism in a Data-flow scheduled Multithreaded processor (JF, QY, RP, CRJ, CZ), pp. 1–4.
DATE-2014-JalleKAQC #design #manycore: Bus designs for time-probabilistic multicore processors (JJ, LK, JA, EQ, FJC), pp. 1–6.
DATE-2014-KamalGAP #approximate #performance #using: Improving efficiency of extensible processors by using approximate custom instructions (MK, AG, AAK, MP), pp. 1–4.
DATE-2014-KimKGH #energy #performance: Utilization-aware load balancing for the energy efficient operation of the big.LITTLE processor (MK, KK, JRG, SH), pp. 1–4.
DATE-2014-KufelWHAWM #embedded: Clock-modulation based watermark for protection of embedded processors (JK, PRW, SH, BMAH, PNW, JM), pp. 1–6.
DATE-2014-KumarYBT #distributed #effectiveness #named: COOLIP: Simple yet effective job allocation for distributed thermally-throttled processors (PK, HY, IB, LT), pp. 1–4.
DATE-2014-NathanS #detection #fault #low cost #named: Nostradamus: Low-cost hardware-only error detection for processor cores (RN, DJS), pp. 1–6.
DATE-2014-RiefertCSBRB #approach #automation #effectiveness #fault #functional #generative #testing: An effective approach to automatic functional processor test generation for small-delay faults (AR, LMC, MS, PB, MSR, BB), pp. 1–6.
DATE-2014-TsaiCCC #3d #configuration management #memory management #multi: Scenario-aware data placement and memory area allocation for Multi-Processor System-on-Chips with reconfigurable 3D-stacked SRAMs (MLT, YJC, YTC, RHC), pp. 1–6.
DATE-2014-WangXWCWW #manycore #power management: Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors (XW, JX, ZW, KJC, XW, ZW), pp. 1–4.
DATE-2014-YasinSE #manycore #polynomial: Unified, ultra compact, quadratic power proxies for multi-core processors (MY, AS, IAME), pp. 1–4.
DATE-2014-ZhangWSX #clustering: Lifetime holes aware register allocation for clustered VLIW processors (XZ, HW, HS, JX), pp. 1–4.
SIGMOD-2014-ChandramouliG: Patience is a virtue: revisiting merge and sort on modern processors (BC, JG), pp. 731–742.
VLDB-2015-ChandramouliGBDPTW14 #incremental #named #query: Trill: A High-Performance Incremental Query Processor for Diverse Analytics (BC, JG, MB, RD, JCP, JFT, JW), pp. 401–412.
VLDB-2015-SridharanP14 #profiling: Profiling R on a Contemporary Processor (SS, JMP), pp. 173–184.
LATA-2014-ArroyoCMP #network: Networks of Polarized Evolutionary Processors Are Computationally Complete (FA, SGC, VM, SP), pp. 101–112.
LATA-2014-SeidlK #analysis #data flow #interprocedural #xml: Interprocedural Information Flow Analysis of XML Processors (HS, MK), pp. 34–61.
KDIR-2014-Bleiweiss #execution #machine learning #using: SoC Processor Discovery for Program Execution Matching Using Unsupervised Machine Learning (AB), pp. 192–201.
SEKE-2014-YangKSWF #named #refactoring: RefactoringScript: A Script and Its Processor for Composite Refactoring (LY, TK, KS, HW, YF), pp. 711–716.
ASPLOS-2014-MorrisonA #bound: Fence-free work stealing on bounded TSO processors (AM, YA), pp. 413–426.
CGO-2014-BrankovicSGG #simulation: Warm-Up Simulation Methodology for HW/SW Co-Designed Processors (AB, KS, EG, AG), p. 284.
HPCA-2014-EmmaBHKPYHBM #3d: 3D stacking of high-performance processors (PGE, AB, MBH, KK, VP, RY, AH, PB, JHM), pp. 500–511.
HPCA-2014-GopeL: Atomic SC for simple in-order processors (DG, MHL), pp. 404–415.
HPCA-2014-HayengaNL #architecture #execution #named #performance: Revolver: Processor architecture for power efficient loop execution (MH, VRKN, MHL), pp. 591–602.
HPCA-2014-JiaSM #memory management #named #parallel: MRPB: Memory request prioritization for massively parallel processors (WJ, KAS, MM), pp. 272–283.
HPCA-2014-PeraisS: Practical data value speculation for future high-end processors (AP, AS), pp. 428–439.
HPDC-2014-RezaeiCLCM #manycore #named: Snapify: capturing snapshots of offload applications on xeon phi manycore processors (AR, GC, CHL, STC, FM), pp. 1–12.
LCTES-2014-ChaudharyFT #compilation #named #specification: em-SPADE: a compiler extension for checking rules extracted from processor specifications (SC, SF, LT), pp. 105–114.
ASE-2013-0002IP #c #concurrent #named #preprocessor #tool support #verification: CSeq: A concurrency pre-processor for sequential C verification tools (BF, OI, GP), pp. 710–713.
DAC-2013-ChandrikakuttyUTW #hardware #monitoring #network: High-performance hardware monitors to protect network processors from data plane attacks (HC, DU, RT, TW), p. 6.
DAC-2013-ChenWBA #random #reuse #simulation #verification: Simulation knowledge extraction and reuse in constrained random processor verification (WC, LCW, JB, MSA), p. 6.
DAC-2013-ChenXKGHKOA #design #manycore #scalability: Dynamic voltage and frequency scaling for shared resources in multicore processor designs (XC, ZX, HK, PVG, JH, MK, ÜYO, RZA), p. 7.
DAC-2013-LiSARHP #adaptation #embedded #fault #named #runtime: RASTER: runtime adaptive spatial/temporal error resiliency for embedded processors (TL, MS, JAA, SR, JH, SP), p. 7.
DAC-2013-LuYHF0 #named: RISO: relaxed network-on-chip isolation for cloud processors (HL, GY, YH, BF, XL), p. 6.
DAC-2013-MercatiBPRB #manycore #reliability #user interface: Workload and user experience-aware dynamic reliability management in multicore processors (PM, AB, FP, TSR, LB), p. 6.
DAC-2013-TurakhiaRGM #architecture #multi #named #synthesis: HaDeS: architectural synthesis for heterogeneous dark silicon chip multi-processors (YT, BR, SG, DM), p. 7.
DAC-2013-ZhangPFH: Lighting the dark silicon by exploiting heterogeneity on future processors (YZ, LP, XF, YH), p. 7.
DATE-2013-AnanthanarayananGP #detection #fault #low cost #set #using: Low cost permanent fault detection using ultra-reduced instruction set co-processors (SA, SG, HDP), pp. 933–938.
DATE-2013-BernardiBSRB #embedded #fault #identification #online: On-line functionally untestable fault identification in embedded processor cores (PB, MB, ES, MSR, OB), pp. 1462–1467.
DATE-2013-BrandonW #using: Support for dynamic issue width in VLIW processors using generic binaries (AB, SW), pp. 827–832.
DATE-2013-CoppolaFGK #embedded #manycore: From embedded multi-core SoCs to scale-out processors (MC, BF, JG, GK), pp. 947–951.
DATE-2013-ElfadelMA #formal method #industrial #manycore: Closed-loop control for power and thermal management in multi-core processors: formal methods and industrial practice (IME, RM, DA), pp. 1879–1881.
DATE-2013-GaoGB #fault tolerance #scheduling #using: Using explicit output comparisons for fault tolerant scheduling (FTS) on modern high-performance processors (YG, SKG, MAB), pp. 927–932.
DATE-2013-JaninBCDEGLT #design: Designing tightly-coupled extension units for the STxP70 processor (YJ, VB, HC, TD, CE, OAG, VL, TT), pp. 1052–1053.
DATE-2013-KodakaTSYKTXSUTMM #manycore #power management #predict: A near-future prediction method for low power consumption on a many-core processor (TK, AT, SS, AY, TK, TT, HX, TS, HU, JT, TM, NM), pp. 1058–1059.
DATE-2013-LiSRRRAHP #configuration management #named: CSER: HW/SW configurable soft-error resiliency for application specific instruction-set processors (TL, MS, SR, SR, RGR, JAA, JH, SP), pp. 707–712.
DATE-2013-LiYHL #adaptation #named #smarttech #user interface: SmartCap: user experience-oriented power adaptation for smartphone’s application processor (XL, GY, YH, XL), pp. 57–60.
DATE-2013-LyrasRPS #multi #scalability #simulation: Hypervised transient SPICE simulations of large netlists & workloads on multi-processor systems (GL, DR, AP, DS), pp. 655–658.
DATE-2013-ParkCA #energy: Non-speculative double-sampling technique to increase energy-efficiency in a high-performance processor (JP, AC, JAA), pp. 254–257.
DATE-2013-RaghunathanTGM #multi #named #process: Cherry-picking: exploiting process variations in dark-silicon homogeneous chip multi-processors (BR, YT, SG, DM), pp. 39–44.
DATE-2013-RahimiMBGB #clustering: Variation-tolerant OpenMP tasking on tightly-coupled processor clusters (AR, AM, PB, RKG, LB), pp. 541–546.
DATE-2013-RajovicRVGPR #case study #energy #experience #mobile #performance: Experiences with mobile processors for energy efficient HPC (NR, AR, JV, IG, NP, AR), pp. 464–468.
DATE-2013-RaminiGBB #3d #analysis #manycore #power management #using: Contrasting wavelength-routed optical NoC topologies for power-efficient 3D-stacked multicore processors using physical-layer analysis (LR, PG, SB, DB), pp. 1589–1594.
DATE-2013-RizkBJMA #case study #design: Statically-scheduled application-specific processor design: a case-study on MMSE MIMO equalization (MR, AB, MJ, YM, YA), pp. 677–680.
DATE-2013-ShengWLY #named #parallel: SPaC: a segment-based parallel compression for backup acceleration in nonvolatile processors (XS, YW, YL, HY), pp. 865–868.
DATE-2013-WangSCC #design #embedded #estimation #performance #reliability: Accurate and efficient reliability estimation techniques during ADL-driven embedded processor design (ZW, KS, CC, AC), pp. 547–552.
DATE-2013-XydisPS #configuration management: Thermal-aware datapath merging for coarse-grained reconfigurable processors (SX, GP, CS), pp. 1649–1654.
DATE-2013-YetimMM #streaming: Extracting useful computation from error-prone processors for streaming applications (YY, MM, SM), pp. 202–207.
DATE-2013-ZhuTSHSS #communication: A 100 GOPS ASP based baseband processor for wireless communication (ZZ, ST, YS, JH, GS, JS), pp. 121–124.
VLDB-2013-NajafiSJ #flexibility #query: Flexible Query Processor on FPGAs (MN, MS, HAJ), pp. 1310–1313.
VLDB-2013-ZhongH #graph #parallel: Parallel Graph Processing on Graphics Processors Made Easy (JZ, BH), pp. 1270–1273.
AdaEurope-2013-KampenhoutH #deployment #manycore #modelling: Model-Based Deployment of Mission-Critical Spacecraft Applications on Multicore Processors (JRvK, RH), pp. 35–50.
HILT-2013-MichellMP #manycore #programming #realtime: Real-time programming on accelerator many-core processors (SM, BM, LMP), pp. 23–36.
SAC-PL-J-2010-RodriguesNPM13 #semantics: Preserving the original MPI semantics in a virtualized processor environment (ERR, POAN, JP, CLM), pp. 412–421.
HPCA-2013-AbeyratneDLSGDBM #scalability #symmetry #towards: Scaling towards kilo-core processors with asymmetric high-radix topologies (NA, RD, QL, KS, BG, RGD, DB, TNM), pp. 496–507.
HPCA-2013-AframZG #implementation: A group-commit mechanism for ROB-based processors implementing the X86 ISA (FA, HZ, KG), pp. 47–58.
HPCA-2013-CragoALP #energy #hybrid #latency #parallel #robust: Hybrid latency tolerance for robust energy-efficiency on 1000-core data parallel processors (NCC, OA, SSL, SJP), pp. 294–305.
HPCA-2013-GuevaraLL #navigation: Navigating heterogeneous processors with market mechanisms (MG, BL, BCL), pp. 95–106.
LCTES-2013-FinlaysonDGUWST #performance #pipes and filters: Improving processor efficiency by statically pipelining instructions (IF, BD, PG, GRU, DBW, MS, GST), pp. 33–44.
PPoPP-2013-DiamosWWLY #algorithm #multi #relational: Relational algorithms for multi-bulk-synchronous processors (GFD, HW, JW, AL, SY), pp. 301–302.
PPoPP-2013-MorrisonA #concurrent #performance: Fast concurrent queues for x86 processors (AM, YA), pp. 103–112.
SOSP-2013-ClementsKZMK #commutative #design #manycore #scalability: The scalable commutativity rule: designing scalable software for multicore processors (ATC, MFK, NZ, RTM, EK), pp. 1–17.
DAC-2012-CheC #embedded #manycore: Unrolling and retiming of stream applications onto embedded multicore processors (WC, KSC), pp. 1272–1277.
DAC-2012-GhasemiSSK #effectiveness #power management: Cost-effective power delivery to support per-core voltage domains for power-constrained processors (HRG, AAS, MJS, NSK), pp. 56–61.
DAC-2012-HoffmannHKLMMNSSACD #self: Self-aware computing in the Angstrom processor (HH, JH, GK, EL, MM, JEM, SMN, MES, YS, AA, APC, SD), pp. 259–264.
DAC-2012-JiangZZY #embedded #multi #performance #scalability: Constructing large and fast multi-level cell STT-MRAM based cache for embedded processors (LJ, BZ, YZ, JY), pp. 907–912.
DAC-2012-RajendiranAPTG #reliability #set: Reliable computing with ultra-reduced instruction set co-processors (AR, SA, HDP, MVT, SG), pp. 697–702.
DAC-2012-RanieriVCAV #algorithm #manycore #named: EigenMaps: algorithms for optimal thermal maps extraction and sensor placement on multicore processors (JR, AV, AC, DA, MV), pp. 636–641.
DAC-2012-SartoriK #compilation #energy #performance: Compiling for energy efficiency on timing speculative processors (JS, RK), pp. 1301–1308.
DAC-2012-SloanSK #design #on the #probability: On software design for stochastic processors (JS, JS, RK), pp. 918–923.
DATE-2012-ChatziparaskevasBP #difference #finite #parallel #using: An FPGA-based parallel processor for Black-Scholes option pricing using finite differences schemes (GC, AB, IP), pp. 709–714.
DATE-2012-JovicYMELA #hybrid #simulation: Hybrid simulation for extensible processor cores (JJ, SY, LGM, JFE, RL, GA), pp. 288–291.
DATE-2012-KakoeeLB #architecture #clustering #communication #latency: A resilient architecture for low latency communication in shared-L1 processor clusters (MRK, IL, LB), pp. 887–892.
DATE-2012-KamalASP #approach #architecture #process: An architecture-level approach for mitigating the impact of process variations on extensible processors (MK, AAK, SS, MP), pp. 467–472.
DATE-2012-LiRP #embedded #hardware #named: Reli: Hardware/software Checkpoint and Recovery scheme for embedded processors (TL, RGR, SP), pp. 875–880.
DATE-2012-RosiereDDW #design: An out-of-order superscalar processor on FPGA: The ReOrder Buffer design (MR, JLD, ND, FW), pp. 1549–1554.
DATE-2012-SabenaRS #algorithm #testing: A new SBST algorithm for testing the register file of VLIW processors (DS, MSR, LS), pp. 412–417.
DATE-2012-SinghNL #generative #smt #testing: Hazard driven test generation for SMT processors (PS, VN, DLL), pp. 256–259.
DATE-2012-SinkarWK #manycore #optimisation #performance: Workload-aware voltage regulator optimization for power efficient multi-core processors (AAS, HW, NSK), pp. 1134–1137.
DATE-2012-Sun #automation #embedded #functional #generative #modelling: Automatic generation of functional models for embedded processor extensions (FS), pp. 304–307.
DATE-2012-WangLLZLSCY #architecture: A compression-based area-efficient recovery architecture for nonvolatile processors (YW, YL, YL, DZ, SL, BS, MFC, HY), pp. 1519–1524.
DATE-2012-ZuluagaBT #case study #design #predict #trade-off: Predicting best design trade-offs: A case study in processor customization (MZ, EVB, NPT), pp. 1030–1035.
DocEng-2012-NetoPS #hypermedia: TAL processor for hypermedia applications (CdSSN, HFP, LFGS), pp. 69–78.
ASPLOS-2012-LinWLZ #named #power management #smarttech #using: Reflex: using low-power processors in smartphones without knowing them (FXL, ZW, RL, LZ), pp. 13–24.
ASPLOS-2012-PanneerselvamS #named #operating system: Chameleon: operating system support for dynamic processors (SP, MMS), pp. 99–110.
ASPLOS-2012-RadojkovicCMVPCNV #approach #parallel #statistics #thread: Optimal task assignment in multithreaded processors: a statistical approach (PR, VC, MM, JV, AP, FJC, MN, MV), pp. 235–248.
CGO-2012-KerrDY #compilation #kernel: Dynamic compilation of data-parallel kernels for vector processors (AK, GFD, SY), pp. 23–32.
HPCA-2012-LinMHSC #named #performance: Parabix: Boosting the efficiency of text processing on commodity processors (DL, NM, KSH, AS, RDC), pp. 373–384.
HPCA-2012-QianST #design #execution #named #smt: BulkSMT: Designing SMT processors for atomic-block execution (XQ, BS, JT), pp. 153–164.
HPCA-2012-VegaBBDFJM #architecture: Architectural perspectives of future wireless base stations based on the IBM PowerEN™ processor (AV, PB, AB, JHD, MF, CJ, RKM), pp. 423–432.
HPDC-2012-GeorgakoudisLN #manycore #migration #summary #symmetry: Dynamic binary rewriting and migration for shared-ISA asymmetric, multicore processors: summary (GG, SL, DSN), pp. 127–128.
ISMM-2012-ZhouD #configuration management #locality #manycore #memory management #policy: Memory management for many-core processors with software configurable locality policies (JZ, BD), pp. 3–14.
LCTES-2012-KyleBFLT #embedded #manycore #set #simulation #using: Efficiently parallelizing instruction set simulation of embedded multi-core processors using region-based just-in-time dynamic binary translation (SCK, IB, BF, HL, NPT), pp. 21–30.
PPoPP-2012-BaghsorkhiGDH #evaluation #memory management #parallel #performance #thread: Efficient performance evaluation of memory hierarchy for highly multithreaded graphics processors (SSB, IG, MD, WmWH), pp. 23–34.
DAC-2011-AdirGLNSSZ #concurrent #multi #named #thread: Threadmill: a post-silicon exerciser for multi-threaded processors (AA, MG, SL, AN, GS, VS, AZ), pp. 860–865.
DAC-2011-AdirNSZMS #validation #verification: Leveraging pre-silicon verification resources for the post-silicon validation of the IBM POWER7 processor (AA, AN, GS, AZ, CM, JS), pp. 569–574.
DAC-2011-BailisRGBS #injection #named: Dimetrodon: processor-level preventive thermal management via idle cycle injection (PB, VJR, SG, DMB, MIS), pp. 89–94.
DAC-2011-BurnsCKPWS #3d #challenge #design: Design, CAD and technology challenges for future processors: 3D perspectives (JB, GC, EK, RP, JDW, MS), p. 212.
DAC-2011-CheC #compilation #embedded #manycore #memory management #source code: Compilation of stream programs onto scratchpad memory based embedded multicore processors through retiming (WC, KSC), pp. 122–127.
DAC-2011-ClemonsJPSA #embedded #feature model #named: EFFEX: an embedded processor for computer vision based feature extraction (JC, AJ, RP, SS, TMA), pp. 1020–1025.
DAC-2011-NadeemBS #embedded #java #named: RJOP: a customized Java processor for reactive embedded systems (MN, MBA, ZS), pp. 1038–1043.
DAC-2011-Paulin #challenge #industrial #multi #perspective #programming: Programming challenges & solutions for multi-processor SoCs: an industrial perspective (PGP), pp. 262–267.
DAC-2011-ThieleSYB #analysis #embedded #multi #synthesis: Thermal-aware system analysis and software synthesis for embedded multi-processors (LT, LS, HY, IB), pp. 268–273.
DATE-2011-AhmedSBH #configuration management #multi #named #runtime: mRTS: Run-time system for reconfigurable processors with multi-grained instruction-set extensions (WA, MS, LB, JH), pp. 1554–1559.
DATE-2011-AsadiniaMTS #using: Supporting non-contiguous processor allocation in mesh-based CMPs using virtual point-to-point links (MA, MM, AT, HSA), pp. 413–418.
DATE-2011-BernardC #power management: A low-power VLIW processor for 3GPP-LTE complex numbers processing (CB, FC), pp. 234–239.
DATE-2011-Furber #architecture: Biologically-inspired massively-parallel architectures — Computing beyond a million processors (SBF), p. 1.
DATE-2011-GizopoulosPARHSMBV #architecture #detection #fault #manycore #online: Architectures for online error detection and recovery in multicore processors (DG, MP, SVA, PR, SKSH, DJS, AM, AB, XV), pp. 533–538.
DATE-2011-HanumaiahV #manycore #realtime: Reliability-aware thermal management for hard real-time applications on multi-core processors (VH, SBKV), pp. 137–142.
DATE-2011-HuangWSLXL #embedded #low cost: A specialized low-cost vectorized loop buffer for embedded processors (LH, ZW, LS, HL, NX, CL), pp. 1200–1203.
DATE-2011-KolpeZS #clustering #manycore #power management: Enabling improved power management in multicore processors through clustered DVFS (TK, AZ, SSS), pp. 293–298.
DATE-2011-LeupersEMSTC #manycore #towards: Virtual Manycore platforms: Moving towards 100+ processor cores (RL, LE, GM, FS, NPT, XC), pp. 715–720.
DATE-2011-LoCWT #modelling #performance #simulation: Cycle-count-accurate processor modeling for fast and accurate system-level simulation (CKL, LCC, MHW, RST), pp. 341–346.
DATE-2011-LungHKC #3d #manycore #online #optimisation #throughput: Thermal-aware on-line task allocation for 3D multi-core processor throughput optimization (CLL, YLH, DMK, SCC), pp. 8–13.
DATE-2011-MichelFP #embedded #simulation: Speeding-up SIMD instructions dynamic binary translation in embedded processor simulation (LM, NF, FP), pp. 277–280.
DATE-2011-MuWLLZCXD #embedded #performance: Evaluating the potential of graphics processors for high performance embedded computing (SM, CW, ML, DL, MZ, XC, XX, YD), pp. 709–714.
DATE-2011-PenolazziSH #energy #multi #performance #predict: Predicting bus contention effects on energy and performance in multi-processor SoCs (SP, IS, AH), pp. 1196–1199.
DATE-2011-RahimiLKB #clustering #network: A fully-synthesizable single-cycle interconnection network for Shared-L1 processor clusters (AR, IL, MRK, LB), pp. 491–496.
DATE-2011-ShafiqueBAH #configuration management #manycore #resource management #runtime: Minority-Game-based resource allocation for run-time reconfigurable multi-core processors (MS, LB, WA, JH), pp. 1261–1266.
DATE-2011-VissersNN #interface #realtime #synthesis #tool support #using: Building real-time HDTV applications in FPGAs using processors, AXI interfaces and high level synthesis tools (KAV, SN, JN), pp. 848–850.
SIGMOD-2011-MarcusWKMM #query: Demonstration of Qurk: a query processor for humanoperators (AM, EW, DRK, SM, RCM), pp. 1315–1318.
SIGMOD-2011-SenellartS #approximate #lightweight #named #probability #query: ProApproX: a lightweight approximation query processor over probabilistic trees (PS, AS), pp. 1295–1298.
VLDB-2011-HeY #transaction: High-throughput transaction executions on graphics processors (BH, JXY), pp. 314–325.
VLDB-2011-SewallCKSD #architecture #manycore #named #parallel: PALM: Parallel Architecture-Friendly Latch-Free Modifications to B+ Trees on Many-Core Processors (JS, JC, CK, NS, PD), pp. 795–806.
PLDI-2011-PrasadAG #automation #compilation #execution #matlab #source code: Automatic compilation of MATLAB programs for synergistic execution on heterogeneous processors (AP, JA, RG), pp. 152–163.
AFL-2011-ManeaT #network: Accepting Networks of Evolutionary Processors with Subregular Filters (FM, BT), pp. 300–314.
DLT-2011-Manea #network: Deciding Networks of Evolutionary Processors (FM), pp. 337–349.
LATA-2011-DassowMT #network: Networks of Evolutionary Processors with Subregular Filters (JD, FM, BT), pp. 262–273.
DUXU-v1-2011-Hasan #multi #online #visual notation #word: Multi-language Online Word Processor for Learners and the Visually Impaired (SIH), pp. 256–260.
CIKM-2011-TomasATV #named #query #scalability: RoSeS: a continuous query processor for large-scale RSS filtering and aggregation (JCT, BA, NT, DV), pp. 2549–2552.
PADL-2011-Kaivola #execution #framework #functional #validation: Intel CoreTM i7 Processor Execution Engine Validation in a Functional Language Based Formal Framework (RK), p. 1.
SAC-2011-BiancoGH #approach #manycore #parallel #performance: A fast approach for parallel deduplication on multicore processors (GDB, RdMG, CAH), pp. 1027–1032.
SAC-2011-Jaghoori #multi #question #scheduling: From nonpreemptive to preemptive scheduling: from single-processor to multi-processor? (MMJ), pp. 717–722.
SAC-2011-KalendarJTD #architecture #novel: Novel processor architecture for modified advanced routing in NGN (MK, DJ, AT, GD), pp. 486–491.
SAC-2011-MitakeKCN #embedded #manycore #realtime: Coexisting real-time OS and general purpose OS on an embedded virtualization layer for a multicore processor (HM, YK, AC, TN), pp. 629–630.
SAC-2011-TianXLC #optimisation #order: Loop fusion and reordering for register file optimization on stream processors (WT, CJX, ML, EC), pp. 560–565.
ASPLOS-2011-KamruzzamanST #manycore #migration #thread #using: Inter-core prefetching for multicore processors using migrating helper threads (MK, SS, DMT), pp. 393–404.
ASPLOS-2011-SinghMNMM #exception #memory management #performance: Efficient processor support for DRFx, a memory model with exceptions (AS, DM, SN, TDM, MM), pp. 53–66.
CGO-2011-SondagR #manycore #symmetry: Phase-based tuning for better utilization of performance-asymmetric multicore processors (TS, HR), pp. 11–20.
HPCA-2011-AndersonFCE #architecture #javascript #mobile: Checked Load: Architectural support for JavaScript type-checking on mobile processors (OA, EF, LC, SJE), pp. 419–430.
HPCA-2011-GhasemiDK #architecture #using: Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors (HRG, SCD, NSK), pp. 38–49.
HPCA-2011-MadanBBA #manycore #power management: A case for guarded power gating for multi-core processors (NM, AB, PB, MA), pp. 291–300.
PPoPP-2011-DotsenkoBLG #fourier #performance: Auto-tuning of fast fourier transform on graphics processors (YD, SSB, BL, NKG), pp. 257–266.
DAC-2010-CohenR #compilation #embedded #manycore: Processor virtualization and split compilation for heterogeneous multicore embedded systems (AC, ER), pp. 102–107.
DAC-2010-HaquePJP #approach #embedded #named #performance #policy #simulation: SCUD: a fast single-pass L1 cache simulation approach for embedded processors with round-robin replacement policy (MSH, JP, AJ, SP), pp. 356–361.
DAC-2010-HePKYALC #energy #named #throughput: Xetal-Pro: an ultra-low energy and high throughput SIMD processor (YH, YP, RPK, ZY, AAA, SML, HC), pp. 543–548.
DAC-2010-KahngKKS #design #power management: Recovery-driven design: a power minimization methodology for error-tolerant processor modules (ABK, SK, RK, JS), pp. 825–830.
DAC-2010-KochteSWZ #fault #manycore #performance #simulation: Efficient fault simulation on many-core processors (MAK, MS, HJW, CGZ), pp. 380–385.
DAC-2010-MarianiBPJZS #design #multi: A correlation-based design space exploration methodology for multi-processor systems-on-chip (GM, AB, GP, JJ, VZ, CS), pp. 120–125.
DAC-2010-NowrozCR #monitoring: Thermal monitoring of real processors: techniques for sensor allocation and full characterization (ANN, RC, SR), pp. 56–61.
DAC-2010-ParkBWM #debugging #graph #locality #named #using: BLoG: post-silicon bug localization in processors using bug localization graphs (SBP, AB, HW, SM), pp. 368–373.
DAC-2010-SridharanM #embedded #power management #realtime #reliability: Reliability aware power management for dual-processor real-time embedded systems (RS, RNM), pp. 819–824.
DAC-2010-ZhangC #embedded: Thermal aware task sequencing on embedded processors (SZ, KSC), pp. 585–590.
DATE-2010-ChePC #compilation #manycore #source code: Compilation of stream programs for multicore processors that incorporate scratchpad memories (WC, AP, KSC), pp. 1118–1123.
DATE-2010-GrottesiMRB #animation #parallel: Parallel subdivision surface rendering and animation on the Cell BE processor (RG, SM, MR, LB), pp. 178–183.
DATE-2010-HaquePJP #approach #embedded #named #performance #policy #simulation: DEW: A fast level 1 cache simulation approach for embedded processors with FIFO replacement policy (MSH, JP, AJ, SP), pp. 496–501.
DATE-2010-HuangX #framework #named #reliability #simulation: AgeSim: A simulation framework for evaluating the lifetime reliability of processor-based SoCs (LH, QX), pp. 51–56.
DATE-2010-MayWBZSHZT #agile #multi #prototype: A rapid prototyping system for error-resilient multi-processor systems-on-chip (MM, NW, AB, JZ, WS, AH, DZ, JT), pp. 375–380.
DATE-2010-MuZZLDZ: IP routing processing with graphic processors (SM, XZ, NZ, JL, YSD, SZ), pp. 93–98.
DATE-2010-NarayananSKJ #probability #scalability: Scalable stochastic processors (SN, JS, RK, DLJ), pp. 335–338.
DATE-2010-RaabBHLSESE #design #power management: Low power design of the X-GOLD® SDR 20 baseband processor (WR, JB, JAUH, DL, MS, HE, JUS, GE), pp. 792–793.
DATE-2010-WangXY #scheduling: Reuse-aware modulo scheduling for stream processors (LW, JX, XY), pp. 1112–1117.
DATE-2010-WongAN #configuration management: Dynamically reconfigurable register file for a softcore VLIW processor (SW, FA, FN), pp. 969–972.
DATE-2010-ZhangYDHRL #manycore #symmetry: Performance-asymmetry-aware topology virtualization for defect-tolerant NoC-based many-core processors (LZ, YY, JD, YH, SR, XL), pp. 1566–1571.
DocEng-2010-OllisBB #documentation #using: Optimized reprocessing of documents using stored processor state (JAO, DFB, SRB), pp. 135–138.
VLDB-2010-FangHL #database: Database Compression on Graphics Processors (WF, BH, QL), pp. 670–680.
ITiCSE-2010-IlbeyiN #named #visualisation: VCache: visualization applet for processor caches (BI, JAN), p. 304.
TACAS-2010-DonaldsonKR #analysis #automation #manycore #memory management: Automatic Analysis of Scratch-Pad Memory Code for Heterogeneous Multicore Processors (AFD, DK, PR), pp. 280–295.
ICALP-v1-2010-GuptaKP #scheduling: Scalably Scheduling Power-Heterogeneous Processors (AG, RK, KP), pp. 312–323.
IFL-2010-BoeijinkHK #functional #lazy evaluation: Introducing the PilGRIM: A Processor for Executing Lazy Functional Languages (AB, PKFH, JK), pp. 54–71.
AdaEurope-2010-Baker #manycore #question #realtime #reliability #what: What to Make of Multicore Processors for Reliable Real-Time Systems? (TPB), pp. 1–18.
GPCE-J-2007-FrisbyKWA10 #algebra #combinator: Constructing language processors with algebra combinators (NF, GK, PW, PA), pp. 543–572.
SAC-2010-WeiYKHC #energy #manycore #realtime #scheduling: Energy-efficient real-time scheduling of multimedia tasks on multi-core processors (YHW, CYY, TWK, SHH, YHC), pp. 258–262.
FSE-2010-HuangLZ #concurrent #java #lightweight #multi #named #source code: LEAP: lightweight deterministic multi-processor replay of concurrent java programs (JH, PL, CZ), pp. 207–216.
FSE-2010-HuangLZ10a #concurrent #java #lightweight #multi #named #source code: LEAP: lightweight deterministic multi-processor replay of concurrent java programs (JH, PL, CZ), pp. 385–386.
ASPLOS-2010-EyermanE #modelling #probability #scheduling #smt: Probabilistic job symbiosis modeling for SMT processor scheduling (SE, LE), pp. 91–102.
ASPLOS-2010-Mesa-MartinezAR #behaviour: Characterizing processor thermal behavior (FJMM, EKA, JR), pp. 193–204.
ASPLOS-2010-ZhuravlevBF #manycore #scheduling: Addressing shared resource contention in multicore processors via scheduling (SZ, SB, AF), pp. 129–142.
HPCA-2010-KahngKKS #design #reliability #trade-off: Designing a processor from the ground up to allow voltage/reliability tradeoffs (ABK, SK, RK, JS), pp. 1–11.
LCTES-2010-ShrivastavaLJ #embedded #equation #fault: Cache vulnerability equations for protecting data in embedded processor caches from soft errors (AS, JL, RJ), pp. 143–152.
ICST-2010-SyedRW #fault #hardware #question: Does Hardware Configuration and Processor Load Impact Software Fault Observability? (RAS, BR, LAW), pp. 285–294.
DAC-2009-Anderson #complexity #design #risk management: Beyond innovation: dealing with the risks and complexity of processor design in 22nm (CJA), p. 103.
DAC-2009-BonnyH #named #performance: LICT: left-uncompressed instructions compression technique to improve the decoding performance of VLIW processors (TB, JH), pp. 903–906.
DAC-2009-BordoloiHCM #design #trade-off: Evaluating design trade-offs in customizable processors (UDB, HPH, SC, TM), pp. 244–249.
DAC-2009-ChangMR #architecture #hybrid #process #video: A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors (IJC, DM, KR), pp. 670–675.
DAC-2009-ChenJ #manycore #performance #scheduling: Efficient program scheduling for heterogeneous multi-core processors (JC, LKJ), pp. 927–930.
DAC-2009-HanumaiahRVC #constraints #manycore #throughput: Throughput optimal task allocation under thermal constraints for multi-core processors (VH, RR, SBKV, KSC), pp. 776–781.
DAC-2009-LeeK #manycore #optimisation #throughput #using: Optimizing throughput of power- and thermal-constrained multicore processors using DVFS and per-core power-gating (JL, NSK), pp. 47–50.
DAC-2009-ThorolfssonGF #3d #automation #case study #design: Design automation for a 3DIC FFT processor for synthetic aperture radar: a case study (TT, KG, PDF), pp. 51–56.
DAC-2009-VishnoiPB #debugging #online: Online cache state dumping for processor debug (AV, PRP, MB), pp. 358–363.
DAC-2009-YooYC #design #memory management #multi #performance: Multiprocessor System-on-Chip designs with active memory processors for higher memory efficiency (JhY, SY, KC), pp. 806–811.
DAC-2009-ZengYGP #manycore #named: MPTLsim: a simulator for X86 multicore processors (HZ, MTY, KG, DVP), pp. 226–231.
DATE-2009-AhmedERCST #performance #pipes and filters #programmable #reduction: Exploration of power reduction and performance enhancement in LEON3 processor with ESL reprogrammable eFPGA in processor pipeline and as a co-processor (SZA, JE, LR, JBC, GS, LT), pp. 184–189.
DATE-2009-BauerSH #architecture #configuration management #design: Cross-architectural design space exploration tool for reconfigurable processors (LB, MS, JH), pp. 958–963.
DATE-2009-ChangHL #adaptation #concurrent #embedded #manycore #named #testing: pTest: An adaptive testing tool for concurrent software on embedded multicore processors (SWC, KYH, JKL), pp. 1012–1017.
DATE-2009-FytrakiP #configuration management: ReSim, a trace-driven, reconfigurable ILP processor simulator (SF, DNP), pp. 536–541.
DATE-2009-Garnier #challenge #roadmap: Trends and challenges in wireless application processors (PG), p. 603.
DATE-2009-GuanLF #design #scalability #set: Design of an application-specific instruction set processor for high-throughput and scalable FFT (XG, HL, YF), pp. 1302–1307.
DATE-2009-GuntoroG #flexibility #float: A flexible floating-point wavelet transform and wavelet packet processor (AG, MG), pp. 1314–1319.
DATE-2009-GuptaRHWB #approach: An event-guided approach to reducing voltage noise in processors (MSG, VJR, GHH, GYW, DMB), pp. 160–165.
DATE-2009-HanumaiahVC #constraints #manycore #performance: Performance optimal speed control of multi-core processors under thermal constraints (VH, SBKV, KSC), pp. 1548–1551.
DATE-2009-IzosimovPPEP #analysis #embedded #fault tolerance #optimisation: Analysis and optimization of fault-tolerant embedded systems with hardened processors (VI, IP, PP, PE, ZP), pp. 682–687.
DATE-2009-JooKH #architecture #communication: On-chip communication architecture exploration for processor-pool-based MPSoC (YPJ, SK, SH), pp. 466–471.
DATE-2009-KodakaSTONKMUAOKTM #design #implementation #manycore #scalability #thread: Design and implementation of scalable, transparent threads for multi-core media processor (TK, SS, TT, RO, NN, KK, TM, YU, HA, YO, TK, YT, NM), pp. 1035–1039.
DATE-2009-LiFNBPC #architecture #co-evolution #design #detection #ml #parallel #set: Algorithm-architecture co-design of soft-output ML MIMO detector for parallel application specific instruction set processors (ML, RF, DN, BB, LVdP, FC), pp. 1608–1613.
DATE-2009-MadduriVBT #manycore #monitoring: A monitor interconnect and support subsystem for multicore processors (SM, RV, WB, RT), pp. 761–766.
DATE-2009-PaternaBAPDO #adaptation #multi: Adaptive idleness distribution for non-uniform aging tolerance in MultiProcessor Systems-on-Chip (FP, LB, AA, FP, GD, MO), pp. 906–909.
DATE-2009-ReordaVMR #embedded #low cost: A low-cost SEE mitigation solution for soft-processors embedded in Systems on Pogrammable Chips (MSR, MV, CM, RR), pp. 352–357.
DATE-2009-VayrynenSL #execution #fault tolerance #multi #optimisation: Fault-tolerant average execution time optimization for general-purpose multi-processor system-on-chips (MV, VS, EL), pp. 484–489.
DATE-2009-VishnoiPB #debugging: Cache aware compression for processor debug support (AV, PRP, MB), pp. 208–213.
DATE-2009-WagnerB #hardware #manycore #named: Caspar: Hardware patching for multicore processors (IW, VB), pp. 658–663.
SIGMOD-2009-MeiM #adaptation #cost analysis #detection #named #query: ZStream: a cost-based query processor for adaptively detecting composite events (YM, SM), pp. 193–206.
VLDB-2009-LeeDCLZ #database #manycore #named: MCC-DB: Minimizing Cache Conflicts in Multi-core Processors for Databases (RL, XD, FC, QL, XZ), pp. 373–384.
ITiCSE-2009-Almeida-MartinezUV #education #named #visualisation: VAST: a visualization-based educational tool for language processors courses (FJAM, JUF, JÁVI), p. 342.
PEPM-2009-MoretBV09a #embedded #java #named: CProf: customizable calling context cross-profiling for embedded java processors (PM, WB, AV), pp. 161–164.
PLDI-2009-InoueKN #case study #manycore #memory management: A study of memory management for web-based applications on multicore processors (HI, HK, TN), pp. 386–396.
SAS-2009-XiaFL #data flow: Inferring Dataflow Properties of User Defined Table Processors (SX, MF, FL), pp. 19–35.
ICALP-v1-2009-Jansen #constant #scheduling #using: An EPTAS for Scheduling Jobs on Uniform Processors: Using an MILP Relaxation with a Constant Number of Integral Variables (KJ), pp. 562–573.
LATA-2009-MitranaT #network #on the: On Accepting Networks of Evolutionary Processors with at Most Two Types of Nodes (VM, BT), pp. 588–600.
HCI-NT-2009-BeeldersBMD #interface #performance #prototype #using #word: Measuring User Performance for Different Interfaces Using a Word Processor Prototype (TRB, PJB, TM, ED), pp. 395–404.
CIKM-2009-BohmNPW #clustering #using: Density-based clustering using graphics processors (CB, RN, CP, BW), pp. 661–670.
ICML-2009-RainaMN #learning #scalability #using: Large-scale deep unsupervised learning using graphics processors (RR, AM, AYN), pp. 873–880.
SIGIR-2009-TatikondaJCP #manycore #on the #performance: On efficient posting list intersection with multicore processors (ST, FJ, BBC, VP), pp. 738–739.
SAC-2009-ChoB #performance #query #xml: Building an efficient preference XML query processor (SC, WTB), pp. 1585–1586.
ASPLOS-2009-EyermanE #smt #thread: Per-thread cycle accounting in SMT processors (SE, LE), pp. 133–144.
HPCA-2009-DuanLP #architecture #estimation #metric #performance #predict: Versatile prediction and fast estimation of Architectural Vulnerability Factor from processor performance metrics (LD, BL, LP), pp. 129–140.
HPCA-2009-FanKDM #programmable: Bridging the computation gap between programmable processors and hardwired accelerators (KF, MK, GSD, SAM), pp. 313–322.
HPCA-2009-GreskampWKCTCZ #design #named: Blueshift: Designing processors for timing speculation from the ground up (BG, LW, URK, JJC, JT, DC, CBZ), pp. 213–224.
HPCA-2009-HiltonNR #named: iCFP: Tolerating all-level cache misses in in-order processors (ADH, SN, AR), pp. 431–442.
HPCA-2009-StephensonZR #lightweight #order: Lightweight predication support for out of order processors (MS, LZ, RR), pp. 201–212.
LCTES-2009-SarkarMRM #manycore #migration #realtime: Push-assisted migration of real-time tasks in multi-core processors (AS, FM, HR, SM), pp. 80–89.
PPoPP-2009-BaskaranVBRRS #effectiveness #manycore #parallel #scheduling: Compiler-assisted dynamic scheduling for effective parallelization of loop nests on multicore processors (MMB, NV, UB, JR, AR, PS), pp. 219–228.
PPoPP-2009-YangHLSS #parallel #recursion: Stack-based parallel recursion on graphics processors (KY, BH, QL, PVS, JS), pp. 299–300.
PPoPP-2009-YangWXDZ #graph #optimisation: Comparability graph coloring for optimizing utilization of stream register files in stream processors (XY, LW, JX, YD, YZ), pp. 111–120.
CAV-2009-KaivolaGNTWPSTFRN #execution #testing #validation #verification: Replacing Testing with Formal Verification in Intel CoreTM i7 Processor Execution Engine Validation (RK, RG, NN, AT, JW, SP, AS, CT, VF, ER, AN), pp. 414–429.
DAC-2008-BauerSH #embedded #runtime #set: Run-time instruction set selection in a transmutable embedded processor (LB, MS, JH), pp. 56–61.
DAC-2008-BournoutianO #design #embedded #reduction: Miss reduction in embedded processors through dynamic, power-friendly cache design (GB, AO), pp. 304–309.
DAC-2008-ChengLLCC #image #named #visual notation: iVisual: an intelligent visual sensor SoC with 2790fps CMOS image sensor and 205GOPS/W vision processor (CCC, CHL, CTL, SCC, LGC), pp. 90–95.
DAC-2008-HomayounPMV #embedded #energy #performance #scalability: Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency (HH, SP, MAM, AVV), pp. 68–71.
DAC-2008-KimKKLY #framework #mobile #recognition: Vision platform for mobile intelligent robot based on 81.6 GOPS object recognition processor (DK, KK, JYK, SL, HJY), pp. 96–101.
DAC-2008-LiBNPC #approach #how #implementation #power management #set: How to let instruction set processor beat ASIC for low power wireless baseband implementation: a system level approach (ML, BB, DN, LVdP, FC), pp. 345–346.
DAC-2008-LuSHWX #effectiveness #multi #optimisation: Customizing computation accelerators for extensible multi-issue processors with effective optimization techniques (YSL, LS, LH, ZW, NX), pp. 197–200.
DAC-2008-ParkM #analysis #debugging #locality #named: IFRA: instruction footprint recording and analysis for post-silicon bug localization in processors (SBP, SM), pp. 373–378.
DAC-2008-SapatnekarHKDKMPS #manycore: Reinventing EDA with manycore processors (SSS, EH, KK, AD, DK, SM, DP, TS), pp. 126–127.
DAC-2008-SenOA #multi #predict #runtime #verification: Predictive runtime verification of multi-processor SoCs in SystemC (AS, VO, MSA), pp. 948–953.
DATE-2008-BauerSKH #embedded #runtime #set: Run-time System for an Extensible Embedded Processor with Dynamic Instruction Set (LB, MS, SK, JH), pp. 752–757.
DATE-2008-BougardSRNADP #array: A Coarse-Grained Array based Baseband Processor for 100Mbps+ Software Defined Radio (BB, BDS, SR, DN, OA, SD, LVdP), pp. 716–721.
DATE-2008-ChenDC #encryption #operating system: Operating System Controlled Processor-Memory Bus Encryption (XC, RPD, ANC), pp. 1154–1159.
DATE-2008-DeleddaMVBGMKRHBCPLMCD #communication #configuration management #design #framework: Design of a HW/SW Communication Infrastructure for a Heterogeneous Reconfigurable Processor (AD, CM, AV, PB, AG, PM, MK, FR, MH, JB, MC, LP, RL, GM, FC, TD), pp. 1352–1357.
DATE-2008-HolzenspiesHKS #multi #runtime #streaming: Run-time Spatial Mapping of Streaming Applications to a Heterogeneous Multi-Processor System-on-Chip (MPSOC) (PKFH, JH, JK, GJMS), pp. 212–217.
DATE-2008-ParkSP #embedded #execution #using: Hiding Cache Miss Penalty Using Priority-based Execution for Embedded Processors (SP, AS, YP), pp. 1190–1195.
DATE-2008-ThoguluvaRC #architecture #performance #programmable #security #using: Efficient Software Architecture for IPSec Acceleration Using a Programmable Security Processor (JT, AR, STC), pp. 1148–1153.
DATE-2008-VemuJAPG #concurrent #detection #fault #logic #low cost: A low-cost concurrent error detection technique for processor control logic (RV, AJ, JAA, SP, RG), pp. 897–902.
DATE-2008-VogtW #configuration management #set: A Reconfigurable Application Specific Instruction Set Processor for Convolutional and Turbo Decoding in a SDR Environment (TV, NW), pp. 38–43.
DATE-2008-WangZHZT #design #multi #reliability: Zero-Efficient Buffer Design for Reliable Network-on-Chip in Tiled Chip-Multi-Processor (JW, HZ, KH, GZ, YT), pp. 792–795.
DATE-2008-WolinskiK #automation #configuration management: Automatic Selection of Application-Specific Reconfigurable Processor Extensions (CW, KK), pp. 1214–1219.
DATE-2008-ZhangHXL #fault #manycore #using: Defect Tolerance in Homogeneous Manycore Processors Using Core-Level Redundancy with Unified Topology (LZ, YH, QX, XL), pp. 891–896.
SIGMOD-2008-HeYFLGLS #relational: Relational joins on graphics processors (BH, KY, RF, ML, NKG, QL, PVS), pp. 511–524.
AFL-2008-Roska #algorithm: Cellular Wave Computers — Algorithms for million processor computers (Abstract) (TR), p. 352.
ICALP-A-2008-BansalCLL #bound #scheduling: Scheduling for Speed Bounded Processors (NB, HLC, TWL, LKL), pp. 409–420.
LATA-2008-AlhazovCMR #hybrid #network: About Universal Hybrid Networks of Evolutionary Processors of Small Size (AA, ECV, CMV, YR), pp. 28–39.
IFL-2008-SvenssonSC #embedded #named #parallel #programming: Obsidian: A Domain Specific Embedded Language for Parallel Programming of Graphics Processors (JS, MS, KC), pp. 156–173.
SOFTVIS-2008-Almeida-MartinezUV #abstract syntax tree #named #syntax #visualisation: VAST: visualization of abstract syntax trees within language processors courses (FJAM, JUF, JÁVI), pp. 209–210.
CIKM-2008-VaidyaL #database #query: Characterization of TPC-H queries for a column-oriented database on a dual-core amd athlon processor (PV, JJL), pp. 1411–1412.
ICML-2008-CatanzaroSK #classification #performance: Fast support vector machine training and classification on graphics processors (BCC, NS, KK), pp. 104–111.
SAC-2008-AtoofianB #behaviour #embedded #latency #memory management: Exploiting program cyclic behavior to reduce memory latency in embedded processors (EA, AB), pp. 1482–1486.
SAC-2008-GuoLPHCDW #design #manycore #memory management: Hierarchical memory system design for a heterogeneous multi-core processor (JG, McL, ZP, LH, FC, KD, ZW), pp. 1504–1508.
SAC-2008-LuCL #embedded #hybrid #self: A hybrid software-based self-testing methodology for embedded processor (THL, CHC, KJL), pp. 1528–1534.
SAC-2008-LuizVS #framework #specification: Formal specification of DSP gateway for data transmission between processor cores of OMAP platform (SODL, GdMV, LDdS), pp. 1545–1549.
SAC-2008-SykoraAS #embedded #pipes and filters: Dynamic configuration of application-specific implicit instructions for embedded pipelined processors (MS, GA, CS), pp. 1509–1516.
ASPLOS-2008-GummarajuCTR #manycore #named #programming #using: Streamware: programming general-purpose multicore processors using streams (JG, JC, YT, MR), pp. 297–307.
CGO-2008-Rubin #challenge #compilation: Issues and challenges in compiling for graphics processors (NR), p. 2.
HPCA-2008-GuptaRSWB #commit #induction #named: DeCoR: A Delayed Commit and Rollback mechanism for handling inductive noise in processors (MSG, KKR, MDS, GYW, DMB), pp. 381–392.
HPCA-2008-SubramaniamPL #dependence #memory management #named #predict #smt: PEEP: Exploiting predictability of memory dependences in SMT processors (SS, MP, GHL), pp. 137–148.
LCTES-2008-HomayounPMV #adaptation #embedded #energy #performance: Improving performance and reducing energy-delay with adaptive resource resizing for out-of-order embedded processors (HH, SP, MAM, AVV), pp. 71–78.
LCTES-2008-WangYXDYTN #optimisation: Optimizing scientific application loops on stream processors (LW, XY, JX, YD, XY, TT, QHN), pp. 161–170.
PPoPP-2008-DiamondRKGGB #algebra #distributed #linear #performance: High performance dense linear algebra on a spatially distributed processor (JRD, BR, SWK, RAvdG, KG, DB), pp. 63–72.
DAC-2007-AdirAFJP #architecture #framework #validation: A Framework for the Validation of Processor Architecture Compliance (AA, SA, LF, IJ, OP), pp. 902–905.
DAC-2007-ChuKCCG #embedded #multi #programming #thread: An Embedded Coherent-Multithreading Multimedia Processor and Its Programming Model (JCC, WCK, SHC, TFC, JIG), pp. 652–657.
DAC-2007-KocKEO #embedded #memory management #multi #using: Reducing Off-Chip Memory Access Costs Using Data Recomputation in Embedded Chip Multi-processors (HK, MTK, EE, ÖÖ), pp. 224–229.
DAC-2007-KumarSCKS #embedded #memory management: A System For Coarse Grained Memory Protection In Tiny Embedded Processors (RK, AS, AC, EK, MBS), pp. 218–223.
DAC-2007-OstlerC #algorithm #approximate #architecture #concurrent #multi #network #thread: Approximation Algorithm for Data Mapping on Block Multi-threaded Network Processor Architectures (CO, KSC), pp. 801–804.
DAC-2007-SolomatnikovFQSKAWHH #generative #multi: Chip Multi-Processor Generator (AS, AF, WQ, OS, KK, ZA, MW, RH, MH), pp. 262–263.
DAC-2007-YuYBY #clustering #network #recursion: Program Mapping onto Network Processors by Recursive Bipartitioning and Refining (JY, JY, LNB, JY), pp. 805–810.
DATE-2007-AtasuDMLOD #constraints #optimisation: Optimizing instruction-set extensible processors under data bandwidth constraints (KA, RGD, OM, WL, CCÖ, GD), pp. 588–593.
DATE-2007-ChattopadhyayAKKLAM #configuration management #design #embedded: Design space exploration of partially re-configurable embedded processors (AC, WA, KK, DK, RL, GA, HM), pp. 319–324.
DATE-2007-FeiS #architecture #monitoring #set: Microarchitectural support for program code integrity monitoring in application-specific instruction set processors (YF, ZJS), pp. 815–820.
DATE-2007-HaastregtK #interactive #optimisation #performance #random #using: Interactive presentation: Feasibility of combined area and performance optimization for superscalar processors using random search (SvH, PMWK), pp. 606–611.
DATE-2007-KimHG #multi #named #simulation #transaction: CATS: cycle accurate transaction-driven simulation with multiple processor simulators (DK, SH, RG), pp. 749–754.
DATE-2007-KumarHHC #configuration management #design #interactive #multi: Interactive presentation: An FPGA design flow for reconfigurable network-based multi-processor systems on chip (AK, AH, JH, HC), pp. 117–122.
DATE-2007-Lysecky #embedded #performance #power management: Low-power warp processor for power efficient high-performance embedded systems (RLL), pp. 141–146.
DATE-2007-MilidonisAPMKG #architecture #interactive #memory management: Interactive presentation: A decoupled architecture of processors with scratch-pad memory hierarchy (AM, NA, VP, HM, AK, CEG), pp. 612–617.
DATE-2007-NarayanasamyCC #fault #predict: Transient fault prediction based on anomalies in processor events (SN, AKC, BC), pp. 1140–1145.
DATE-2007-Naumann #design #evolution #question: Keynote address: Was Darwin wrong? Has design evolution stopped at the RTL level... or will software and custom processors (or system-level design) extend Moore’s law? (AN), p. 2.
DATE-2007-NooriMMIG #adaptation #generative #interactive #multi: Interactive presentation: Generating and executing multi-exit custom instructions for an adaptive extensible processor (HN, FM, KM, KI, MG), pp. 325–330.
DATE-2007-OstlerC #architecture #network: An ILP formulation for system-level application mapping on network processor architectures (CO, KSC), pp. 99–104.
DATE-2007-ParkPBBKD #architecture #embedded #performance #pointer: Register pointer architecture for efficient embedded processors (JP, SBP, JDB, DBS, CK, WJD), pp. 600–605.
DATE-2007-PozziP #future of #question: A future of customizable processors: are we there yet? (LP, PGP), pp. 1224–1225.
DATE-2007-RaghavanLJCVC #embedded #power management #symmetry: Very wide register: an asymmetric register file organization for low power embedded processors (PR, AL, MJ, FC, DV, HC), pp. 1066–1071.
DATE-2007-RhodLC #architecture #performance: A low-SER efficient core processor architecture for future technologies (ELR, CALL, LC), pp. 1448–1453.
DATE-2007-SanchezSSR #automation #effectiveness #generative #interactive #source code: Interactive presentation: An enhanced technique for the automatic generation of effective diagnosis-oriented test programs for processor (ES, MS, GS, MSR), pp. 1158–1163.
DATE-2007-SheldonVL #design #interactive #paradigm #using: Interactive presentation: Soft-core processor customization using the design of experiments paradigm (DS, FV, SL), pp. 821–826.
DATE-2007-WatanabeKINN #constraints #energy #interactive #multi #performance #scheduling: Interactive presentation: Task scheduling under performance constraints for reducing the energy consumption of the GALS multi-processor SoC (RW, MK, MI, HN, TN), pp. 797–802.
DATE-2007-YeungTB #framework #interactive #interface #multi #novel: Interactive presentation: Novel test infrastructure and methodology used for accelerated bring-up and in-system characterization of the multi-gigahertz interfaces on the cell processor (PY, AT, PB), pp. 725–730.
DATE-2007-ZhuSD #functional #interactive #pipes and filters #validation: Interactive presentation: Functional and timing validation of partially bypassed processor pipelines (QZ, AS, ND), pp. 1164–1169.
SIGMOD-2007-FangHLYGLS #named #query #using: GPUQP: query co-processing using graphics processors (RF, BH, ML, KY, NKG, QL, PVS), pp. 1061–1063.
SIGMOD-2007-HeLLY #in memory #named #query: EaseDB: a cache-oblivious in-memory query processor (BH, YL, QL, DY), pp. 1064–1066.
VLDB-2007-GedikBY #named #performance #sorting: CellSort: High Performance Sorting on the Cell Processor (BG, RB, PSY), pp. 1286–1207.
VLDB-2007-GedikYB: Executing Stream Joins on the Cell Processor (BG, PSY, RB), pp. 363–374.
VLDB-2007-LiL #mining #multi #optimisation: Optimization of Frequent Itemset Mining on Multiple-Core Processor (EL, LL), pp. 1275–1285.
LATA-2007-AlhazovMR #network #predict: Networks of Evolutionary Processors with Two Nodes Are Unpredictable (AA, CMV, YR), pp. 521–528.
GPCE-2007-WeaverKFA #algebra #combinator: Constructing language processors with algebra combinators (PW, GK, NF, PA), pp. 155–164.
SAC-2007-ChaiZX #java #realtime: Real-time Java processor optimized for RTSJ (ZC, WZ, WX), pp. 1540–1544.
SAC-2007-JinM #network #scheduling: An analytical model for generalized processor sharing scheduling with heterogeneous network traffic (XJ, GM), pp. 198–202.
GTTSE-2007-PielMD #compilation #model transformation #multi: Model Transformations for the Compilation of Multi-processor Systems-on-Chip (ÉP, PM, JLD), pp. 459–473.
CC-2007-ChoAUP #effectiveness #multi #preprocessor #scheduling: Preprocessing Strategy for Effective Modulo Scheduling on Multi-issue Digital Signal Processors (DC, RA, GRU, YP), pp. 16–31.
CGO-2007-Buck #gpu #parallel #programming: GPU Computing: Programming a Massively Parallel Processor (IB), p. 17.
CGO-2007-DaiLH #execution #network #pipes and filters #using: Pipelined Execution of Critical Sections Using Software-Controlled Caching in Network Processors (JD, LL, BH), pp. 312–324.
CGO-2007-KimJMP #compilation: Profile-assisted Compiler Support for Dynamic Predication in Diverge-Merge Processors (HK, JAJ, OM, YNP), pp. 367–378.
HPCA-2007-EyermanE #parallel #policy #smt: A Memory-Level Parallelism Aware Fetch Policy for SMT Processors (SE, LE), pp. 240–249.
HPCA-2007-PuttaswamyL #3d #architecture: Thermal Herding: Microarchitecture Techniques for Controlling Hotspots in High-Performance 3D-Integrated Processors (KP, GHL), pp. 193–204.
HPCA-2007-QuinonesPG #branch #execution #predict: Improving Branch Prediction and Predicated Execution in Out-of-Order Processors (EQ, JMP, AG), pp. 75–84.
LCTES-2007-BennettMFT #automation #embedded #set #text-to-text: Combining source-to-source transformations and processor instruction set extensions for the automated design-space exploration of embedded systems (RVB, ACM, BF, NPT), pp. 83–92.
LCTES-2007-ChenTCLYLL #compilation #distributed #embedded: Enabling compiler flow for embedded VLIW DSP processors with distributed register files (CKC, LHT, SCC, YJL, YPY, CHL, JKL), pp. 146–148.
LCTES-2007-XuT #named: Tetris: a new register pressure control technique for VLIW processors (WX, RT), pp. 113–122.
PPoPP-2007-BarrettAV #evaluation #performance: Performance evaluation of the cray XT3 configured with dual core opteron processors (RFB, SRA, JSV), pp. 148–149.
PPoPP-2007-GuoDLLC #latency #multi #network #thread: Latency hiding through multithreading on a network processor (XG, JD, LL, ZL, PRC), pp. 130–131.
CASE-2006-RaghavanV #optimisation #parallel #product line #scheduling #using: Scheduling Parallel Batch Processors with Incompatible Job Families Using Ant Colony Optimization (NRSR, MV), pp. 507–512.
DAC-2006-AtienzaVPPBMM #framework #multi #performance: A fast HW/SW FPGA-based thermal emulation framework for multi-processor system-on-chip (DA, PGDV, GP, FP, LB, GDM, JMM), pp. 618–623.
DAC-2006-ElbazTSGBM #encryption: A parallelized way to provide data encryption and integrity checking on a processor-memory bus (RE, LT, GS, PG, MB, AM), pp. 506–509.
DAC-2006-HattoriIIYKSYNYKTHAHTSMYHMYHTYIKMYITAAO #mobile #power management: Hierarchical power distribution and power management scheme for a single chip mobile processor (TH, TI, MI, EY, HK, GS, TY, KN, HY, TK, YT, MH, HA, IH, KT, YS, NM, YY, TH, YM, KY, KH, ST, SY, TI, YK, HM, TY, NI, RT, NA, TA, KO), pp. 292–295.
DAC-2006-HuangG #embedded #scalability: Leakage-aware intraprogram voltage scaling for embedded processors (PKH, SG), pp. 364–369.
DAC-2006-InoueIKSE #architecture #mobile #named: VIRTUS: a new processor virtualization architecture for security-oriented next-generation mobile terminals (HI, AI, MK, JS, ME), pp. 484–489.
DAC-2006-JerrayaBP #abstraction #interface #modelling #multi #programming: Programming models and HW-SW interfaces abstraction for multi-processor SoC (AAJ, AB, FP), pp. 280–285.
DAC-2006-LoiASLSB #3d #analysis #performance: A thermally-aware performance analysis of vertically integrated (3-D) processor-memory hierarchy (GLL, BA, NS, SCL, TS, KB), pp. 991–996.
DAC-2006-PsarakisGHPRR #pipes and filters #self: Systematic software-based self-test for pipelined processors (MP, DG, MH, AMP, AR, SR), pp. 393–398.
DAC-2006-RagelP #monitoring #named #reliability #security: IMPRES: integrated monitoring for processor reliability and security (RGR, SP), pp. 502–505.
DAC-2006-ShimizuGKOAMS #verification: Verification of the cell broadband engineTM processor (KS, SG, TK, TO, JA, LM, TS), pp. 338–343.
DAC-2006-WangLLYHWH #design #framework #network #security: A network security processor design based on an integrated SOC design and test platform (CHW, CYL, MSL, JCY, CTH, CWW, SYH), pp. 490–495.
DAC-2006-ZhouP #agile #embedded #low cost #realtime: Rapid and low-cost context-switch through embedded processor customization for real-time and control applications (XZ, PP), pp. 352–357.
DATE-2006-BernardiSSSR #cost analysis #effectiveness: An effective technique for minimizing the cost of processor software-based diagnosis in SoCs (PB, ES, MS, GS, MSR), pp. 412–417.
DATE-2006-BertozziABP #migration #multi: Supporting task migration in multi-processor systems-on-chip: a feasibility study (SB, AA, DB, AP), pp. 15–20.
DATE-2006-ChattopadhyayGKWSILAM #automation #embedded: Automatic ADL-based operand isolation for embedded processors (AC, BG, DK, EMW, OS, HI, RL, GA, HM), pp. 600–605.
DATE-2006-DimondML #automation #memory management #resource management: Automating processor customisation: optimised memory access and resource sharing (RGD, OM, WL), pp. 206–211.
DATE-2006-EyermanEB #design #embedded #performance: Efficient design space exploration of high performance embedded out-of-order processors (SE, LE, KDB), pp. 351–356.
DATE-2006-HerkersdorfS #architecture #flexibility #named: AutoVision: flexible processor architecture for video-assisted driving (AH, WS), p. 556.
DATE-2006-HuangG06a #adaptation #compilation #embedded #power management #scalability: Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities (PKH, SG), pp. 943–944.
DATE-2006-KooM #functional #generative #pipes and filters #testing #using #validation: Functional test generation using property decompositions for validation of pipelined processors (HMK, PM), pp. 1240–1245.
DATE-2006-KranitisMLTPGH #embedded #fault #pipes and filters #testing: Optimal periodic testing of intermittent faults in embedded pipelined processor applications (NK, AM, NL, GT, AMP, DG, CH), pp. 65–70.
DATE-2006-LeupersKKP #configuration management #design #embedded #set #synthesis: A design flow for configurable embedded processors based on optimized instruction set extension synthesis (RL, KK, SK, MP), pp. 581–586.
DATE-2006-MolnosHCE #composition #multi #performance: Compositional, efficient caches for a chip multi-processor (AMM, MJMH, SDC, JTJvE), pp. 345–350.
DATE-2006-ParkESNDP #automation #embedded #generative #performance: Automatic generation of operation tables for fast exploration of bypasses in embedded processors (SP, EE, AS, AN, ND, YP), pp. 1197–1202.
DATE-2006-PaulinPLBBLLL #distributed #modelling #multi #power management: Distributed object models for multi-processor SoC’s, with application to low-power multimedia wireless systems (PGP, CP, ML, EB, OB, DL, BL, DL), pp. 482–487.
DATE-2006-RadhakrishnanGP #multi: Customization of application specific heterogeneous multi-pipeline processors (SR, HG, SP), pp. 746–751.
DATE-2006-RaghavanLJCV #architecture #distributed #multi #thread: Distributed loop controller architecture for multi-threading in uni-threaded VLIW processors (PR, AL, MJ, FC, DV), pp. 339–344.
DATE-2006-RuggieroGBPM #framework #multi #scheduling: Communication-aware allocation and scheduling framework for stream-oriented multi-processor systems-on-chip (MR, AG, DB, FP, MM), pp. 3–8.
DATE-2006-ScharwachterHLAM #hardware #interprocedural #multi #network #optimisation #thread #using: An interprocedural code optimization technique for network processors using hardware multi-threading support (HS, MH, RL, GA, HM), pp. 919–924.
DATE-2006-Schoeberl #java #predict: A time predictable Java processor (MS), pp. 800–805.
DATE-2006-StreubuhrFHTDS #architecture #modelling #multi #performance #realtime: Task-accurate performance modeling in SystemC for real-time multi-processor architectures (MS, JF, CH, JT, RD, TS), pp. 480–481.
DATE-2006-ZhouW #constraints #self: Software-based self-test of processors under power constraints (JZ, HJW), pp. 430–435.
DATE-2006-ZmilyK #embedded #energy #performance: Simultaneously improving code size, performance, and energy in embedded processors (AZ, CK), pp. 224–229.
DATE-DF-2006-AkselrodAA #architecture #debugging #framework #independence #multi #security: Platform independent debug port controller architecture with security protection for multi-processor system-on-chip ICs (DA, AA, YA), pp. 30–35.
DATE-DF-2006-KappenN #implementation: Application specific instruction processor based implementation of a GNSS receiver on an FPGA (GK, TGN), pp. 58–63.
DATE-DF-2006-MadingLPSBEH #architecture #fixpoint: The vector fixed point unit of the synergistic processor element of the cell architecture processor (NM, JL, JP, RS, SB, SE, WH), pp. 244–248.
DATE-DF-2006-SohnWYY #design #fixpoint #mobile #multi: Design and test of fixed-point multimedia co-processor for mobile applications (JHS, JHW, JY, HJY), pp. 249–253.
SIGMOD-2006-BonczGKMRT #named #performance #relational #xquery: MonetDB/XQuery: a fast XQuery processor powered by a relational engine (PAB, TG, MvK, SM, JR, JT), pp. 479–490.
SIGMOD-2006-GovindarajuGKM #database #named #performance #scalability #sorting: GPUTeraSort: high performance graphics co-processor sorting for large database management (NKG, JG, RK, DM), pp. 325–336.
VLDB-2006-AilamakiGHM #query: Query Co-Processing on Commodity Processors (AA, NKG, SH, DM), p. 1267.
SIGAda-2006-ShindiC #benchmark #metric #performance: Evaluate the performance changes of processor simulator benchmarks When context switches are incorporated (RSS, SC), pp. 9–14.
MoDELS-2006-BertolinoBAS #estimation #modelling #network #performance: Modeling and Early Performance Estimation for Network Processor Applications (AB, AB, GDA, ALSV), pp. 753–767.
MoDELS-2006-BertolinoBAS #estimation #modelling #network #performance: Modeling and Early Performance Estimation for Network Processor Applications (AB, AB, GDA, ALSV), pp. 753–767.
SAC-2006-ChoRJ #embedded #on the #realtime #scheduling: On utility accrual processor scheduling with wait-free synchronization for embedded real-time software (HC, BR, EDJ), pp. 918–922.
SAC-2006-DerisB #embedded #predict: Branchless cycle prediction for embedded processors (KJD, AB), pp. 928–932.
SAC-2006-LastovetskyRH #functional #performance: Building the functional performance model of a processor (ALL, RR, RH), pp. 746–753.
SAC-2006-LiH #concurrent #multi #thread: A concurrent reactive Esterel processor based on multi-threading (XL, RvH), pp. 912–917.
SAC-2006-Lo #protocol #smt: Data sharing protocols for SMT processors (SWL), pp. 891–895.
SAC-2006-NooriM #adaptation #embedded #evaluation #performance: Preliminary performance evaluation of an adaptive dynamic extensible processor for embedded applications (HN, KM), pp. 937–938.
LDTA-2006-SierraF #agile #attribute grammar #framework #prolog #prototype: A Prolog Framework for the Rapid Prototyping of Language Processors with Attribute Grammars (JLS, AFV), pp. 19–36.
ASPLOS-2006-LiBH #concurrent #embedded #multi #thread: Mapping esterel onto a multi-threaded embedded processor (XL, MB, RvH), pp. 303–314.
ASPLOS-2006-MillerA #embedded: Software-based instruction caching for embedded processors (JEM, AA), pp. 293–302.
CGO-2006-ChuM #clustering #multi: Compiler-directed Data Partitioning for Multicluster Processors (MLC, SAM), pp. 208–220.
CGO-2006-WentzlaffA #architecture: Constructing Virtual Architectures on a Tiled Processor (DW, AA), pp. 173–184.
HPCA-2006-HuKLS #approach #implementation #performance: An approach for implementing efficient superscalar CISC processors (SH, IK, MHL, JES), pp. 41–52.
HPCA-2006-JosephVT #analysis #linear #modelling #performance: Construction and use of linear regression models for processor performance analysis (PJJ, KV, MJT), pp. 99–108.
HPCA-2006-PenryFHWSAC #parallel #simulation: Exploiting parallelism and structure to accelerate the simulation of chip multi-processors (DAP, DF, DH, RW, GS, DIA, DC), pp. 29–40.
HPCA-2006-PericasCGJV: A decoupled KILO-instruction processor (MP, AC, RG, DAJ, MV), pp. 53–64.
HPCA-2006-SharkeyP #performance #smt: Efficient instruction schedulers for SMT processors (JJS, DVP), pp. 288–298.
ISMM-2006-Hosking #garbage collection #multi: Portable, mostly-concurrent, mostly-copying garbage collection for multi-processors (ALH), pp. 40–51.
LCTES-2006-ChenK #scalability #scheduling: Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor (JJC, TWK), pp. 153–162.
LCTES-2006-ZhuangP #analysis #compilation #concurrent #effectiveness #network #thread: Effective thread management on network processors with compiler analysis (XZ, SP), pp. 72–82.
PPoPP-2006-HuTH #algorithm #manycore #network #parallel #thread: High-performance IPv6 forwarding algorithm for multi-core and multithreaded network processor (XH, XT, BH), pp. 168–177.
DAC-2005-EzerJ #configuration management #verification: Smart diagnostics for configurable processor verification (SE, SJ), pp. 789–794.
DAC-2005-Heidergott #design: SEU tolerant device, circuit and processor design (WH), pp. 5–10.
DAC-2005-KimK05a #evaluation #modelling #performance #pipes and filters #reuse #simulation: Performance simulation modeling for fast evaluation of pipelined scalar processor by evaluation reuse (HYK, TGK), pp. 341–344.
DAC-2005-LuoYYB #design #network #power management #using: Low power network processor design using clock gating (YL, JY, JY, LNB), pp. 712–715.
DAC-2005-PetrovTO #embedded #energy #memory management: Energy-effcient physically tagged caches for embedded processors with virtual memory (PP, DT, AO), pp. 17–22.
DAC-2005-WeiR #configuration management #implementation #power management #trade-off: Implementing low-power configurable processors: practical options and tradeoffs (JW, CR), pp. 706–711.
DAC-2005-WongKP #flexibility #multi: Flexible ASIC: shared masking for multiple media processors (JLW, FK, MP), pp. 909–914.
DATE-2005-AmoryLMM #architecture #multi #reduction #reuse: Test Time Reduction Reusing Multiple Processors in a Network-on-Chip Based Architecture (AMA, ML, FGM, EIM), pp. 62–63.
DATE-2005-BarrettaFSB #clustering #embedded #parallel #thread: Multithreaded Extension to Multicluster VLIW Processors for Embedded Applications (DB, WF, MS, DB), pp. 748–749.
DATE-2005-BomelMB #latency #synthesis: Synchronization Processor Synthesis for Latency Insensitive Systems (PB, EM, EB), pp. 896–897.
DATE-2005-IshiharaF #power management: A Way Memoization Technique for Reducing Power Consumption of Caches in Application Specific Integrated Processors (TI, FF), pp. 358–363.
DATE-2005-KempfDLAMKV #composition #framework #multi #simulation: A Modular Simulation Framework for Spatial and Temporal Task Mapping onto Multi-Processor SoC Platforms (TK, MD, RL, GA, HM, TK, BV), pp. 876–881.
DATE-2005-LyseckyV #case study #clustering #hardware #using: A Study of the Speedups and Competitiveness of FPGA Soft Processor Cores using Dynamic Hardware/Software Partitioning (RLL, FV), pp. 18–23.
DATE-2005-ManoliosS #modelling #performance #refinement #verification: Refinement Maps for Efficient Verification of Processor Models (PM, SKS), pp. 1304–1309.
DATE-2005-MayerSM #debugging #multi: Debug Support, Calibration and Emulation for Multiple Processor and Powertrain Control SoCs (AM, HS, KDMM), pp. 148–152.
DATE-2005-MishraD #functional #generative #pipes and filters #testing #validation: Functional Coverage Driven Test Generation for Validation of Pipelined Processors (PM, NDD), pp. 678–683.
DATE-2005-PapaefstathiouOKKMN #network #queue: Queue Management in Network Processors (IP, TO, GK, CK, IM, AN), pp. 112–117.
DATE-2005-PradeepVBK #agile #on-demand: FPGA based Agile Algorithm-On-Demand Co-Processor (RP, SV, SB, VK), pp. 82–83.
DATE-2005-ReshadiD #generative #modelling #performance #pipes and filters: Generic Pipelined Processor Modeling and High Performance Cycle-Accurate Simulator Generation (MR, NDD), pp. 786–791.
DATE-2005-ShrivastavaDNE #embedded #framework #named: PBExplore: A Framework for Compiler-in-the-Loop Exploration of Partial Bypassing in Embedded Processors (AS, NDD, AN, EE), pp. 1264–1269.
DATE-2005-YuWCHYB #architecture #design #network: Assertion-Based Design Exploration of DVS in Network Processor Architectures (JY, WW, XC, HH, JY, FB), pp. 92–97.
SIGMOD-2005-GovindarajuRM #approximate #mining #performance #using: Fast and Approximate Stream Mining of Quantiles and Frequencies Using Graphics Processors (NKG, NR, DM), pp. 611–622.
VLDB-2005-GhotingBPKNCD #mining: Cache-conscious Frequent Pattern Mining on a Modern Processor (AG, GB, SP, DK, ADN, YKC, PD), pp. 577–588.
VLDB-2005-MoroVT #lightweight #query #xml: Tree-Pattern Queries on a Lightweight XML Processor (MMM, ZV, VJT), pp. 205–216.
VLDB-2005-ZhouCRS #database #multi #performance #thread: Improving Database Performance on Simultaneous Multithreading Processors (JZ, JC, KAR, MS), pp. 49–60.
SAC-2005-DebbabiMT #compilation #embedded #java #virtual machine: Armed E-Bunny: a selective dynamic compiler for embedded Java virtual machine targeting ARM processors (MD, AM, NT), pp. 874–878.
SAC-2005-JuurlinkSV #embedded: Avoiding data conversions in embedded media processors (BHHJ, AS, SV), pp. 901–902.
SAC-2005-MenonS #embedded: A code compression advisory tool for embedded processors (SKM, PS), pp. 863–867.
SAC-2005-WaerdtSIV #estimation #performance: Motion estimation performance of the TM3270 processor (JWvdW, GAS, JPvI, SV), pp. 850–856.
SAC-2005-WengW #network #parallel #profiling: Profiling and mapping of parallel workloads on network processors (NW, TW), pp. 890–896.
CC-2005-EnnalsSM #clustering #manycore #network: Task Partitioning for Multi-core Network Processors (RE, RS, AM), pp. 76–90.
HPCA-2005-ChandraGKS #architecture #multi #predict #thread: Predicting Inter-Thread Cache Contention on a Chip Multi-Processor Architecture (DC, FG, SK, YS), pp. 340–351.
HPCA-2005-Hofstee #architecture #performance: Power Efficient Processor Architecture and The Cell Processor (HPH), pp. 258–262.
HPCA-2005-JacobsonBHBZEEGLST #performance: Stretching the Limits of Clock-Gating Efficiency in Server-Class Processors (HMJ, PB, ZH, AB, VVZ, RJE, LE, JG, DL, BS, JMT), pp. 238–242.
HPCA-2005-Weber #roadmap: Trends in High-Performance Processors (FW), p. 3.
HPCA-2005-WuJMC #adaptation #multi: Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors (QW, PJ, MM, DWC), pp. 178–189.
HPCA-2005-ZhuZ #comparison #memory management #optimisation #performance #smt: A Performance Comparison of DRAM Memory System Optimizations for SMT Processors (ZZ, ZZ), pp. 213–224.
LCTES-2005-KudriavtsevK #generative #permutation: Generation of permutations for SIMD processors (AK, PMK), pp. 147–156.
DAC-2004-BehmLLRV #experience #generative #industrial #testing #verification: Industrial experience with test generation languages for processor verification (MLB, JML, YL, MR, MV), pp. 36–40.
DAC-2004-ChengTM #embedded #named #synthesis: FITS: framework-based instruction-set tuning synthesis for embedded application specific processors (ACC, GST, TNM), pp. 920–923.
DAC-2004-DeleganesBGKSW #integer #logic: Low voltage swing logic circuits for a Pentium 4 processor integer core (DJD, MB, GG, KK, APS, SW), pp. 678–680.
DAC-2004-EkpanyapongMWLL #architecture #design: Profile-guided microarchitectural floorplanning for deep submicron processor design (ME, JRM, TW, HHSL, SKL), pp. 634–639.
DAC-2004-YuM #embedded: Characterizing embedded applications for instruction-set extensible processors (PY, TM), pp. 723–728.
DATE-DF-2004-ChenLHBB #design #network: Utilizing Formal Assertions for System Design of Network Processors (XC, YL, HH, LNB, FB), pp. 126–133.
DATE-DF-2004-ChuDPSL #architecture #tool support: Customisable EPIC Processor: Architecture and Tools (WWSC, RGD, SP, SPS, WL), pp. 236–241.
DATE-DF-2004-PapaefstathiouKZ #network #performance: Software Processing Performance in Network Processors (IP, GK, NZ), pp. 186–191.
DATE-DF-2004-PaulinPBLL #framework #multi #performance: Application of a Multi-Processor SoC Platform to High-Speed Packet Forwarding (PGP, CP, EB, ML, DL), pp. 58–63.
DATE-DF-2004-SchliebuschCLAMSBN #architecture #implementation #synthesis: RTL Processor Synthesis for Architecture Exploration and Implementation (OS, AC, RL, GA, HM, MS, GB, AN), pp. 156–160.
DATE-v1-2004-FummiMPP #integration #multi: Native ISS-SystemC Integration for the Co-Simulation of Multi-Processor SoC (FF, SM, GP, MP), pp. 564–569.
DATE-v1-2004-GoloubevaRV #automation #generative #validation: Automatic Generation of Validation Stimuli for Application-Specific Processors (OG, MSR, MV), pp. 188–193.
DATE-v1-2004-HounsellT #embedded #synthesis: Co-Processor Synthesis: A New Methodology for Embedded Software Acceleration (BIH, RT), pp. 682–683.
DATE-v1-2004-LaurentJSM #analysis #approach #functional #modelling #performance #power management: Functional Level Power Analysis: An Efficient Approach for Modeling the Power Consumption of Complex Processors (JL, NJ, ES, EM), pp. 666–667.
DATE-v1-2004-ManoliosS #automation #liveness #modelling #safety #using #verification #web: Automatic Verification of Safety and Liveness for XScale-Like Processor Models Using WEB Refinements (PM, SKS), pp. 168–175.
DATE-v1-2004-MishraD #functional #generative #graph #pipes and filters: Graph-Based Functional Test Program Generation for Pipelined Processors (PM, ND), pp. 182–187.
DATE-v1-2004-PaschalisG #effectiveness #embedded #online #self #testing: Effective Software-Based Self-Test Strategies for On-Line Periodic Testing of Embedded Processors (AMP, DG), pp. 578–583.
DATE-v1-2004-PatelMP #architecture #energy #memory management #multi #synthesis: Synthesis of Partitioned Shared Memory Architectures for Energy-Efficient Multi-Processor SoC (KP, EM, MP), pp. 700–701.
DATE-v1-2004-QuinnLBA #configuration management #framework #network: A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors (DQ, BL, GB, EMA), pp. 364–371.
DATE-v2-2004-AragonNVB #design #embedded #energy: Energy-Efficient Design for Highly Associative Instruction Caches in Next-Generation Embedded Processors (JLA, DN, AVV, AMB), pp. 1374–1375.
DATE-v2-2004-CheungPHC #equivalence #named #using: MINCE: Matching INstructions Using Combinational Equivalence for Extensible Processor (NC, SP, JH, JC), pp. 1020–1027.
DATE-v2-2004-DziriCWJ #component #design #integration #multi #validation: Unified Component Integration Flow for Multi-Processor SoC Design and Validation (MAD, WOC, FRW, AAJ), pp. 1132–1137.
DATE-v2-2004-HohenauerSKWKLAMBS #c #compilation #generative #modelling: A Methodology and Tool Suite for C Compiler Generation from ADL Processor Models (MH, HS, KK, OW, TK, RL, GA, HM, GB, HvS), pp. 1276–1283.
DATE-v2-2004-KadayifKK #energy #multi: Exploiting Processor Workload Heterogeneity for Reducing Energy Consumption in Chip Multiprocessors (IK, MTK, IK), pp. 1158–1163.
DATE-v2-2004-WieferinkKLAMBN #communication #framework #multi: A System Level Processor/Communication Co-Exploration Methodology for Multi-Processor System-on-Chip Platform (AW, TK, RL, GA, HM, GB, AN), pp. 1256–1263.
DATE-v2-2004-YooYBJD #concept #design #multi #using: Multi-Processor SoC Design Methodology Using a Concept of Two-Layer Hardware-Dependent Software (SY, MWY, AB, AAJ, MDN), pp. 1382–1383.
SIGMOD-2004-GovindarajuLWLM #database #performance #using: Fast Computation of Database Operations using Graphics Processors (NKG, BL, WW, MCL, DM), pp. 215–226.
VLDB-2004-KochSSS #data type #query #scheduling: Schema-based Scheduling of Event Processors and Buffer Minimization for Queries on Structured Data Streams (CK, SS, NS, BS), pp. 228–239.
VLDB-2004-KochSSS04a #named #optimisation #streaming #xml #xquery: FluXQuery: An Optimizing XQuery Processor for Streaming XML Data (CK, SS, NS, BS), pp. 1309–1312.
VLDB-2004-LooHHSS #query: Enhancing P2P File-Sharing with an Internet-Scale Query Processor (BTL, JMH, RH, SS, IS), pp. 432–443.
VLDB-2004-MokbelXAHPH #data type #named #query #realtime: PLACE: A Query Processor for Handling Real-time Spatio-temporal Data Streams (MFM, XX, WGA, SEH, SP, MAH), pp. 1377–1380.
PLDI-2004-ZhuangP #network #parallel #thread: Balancing register allocation across threads for a multithreaded network processor (XZ, SP), pp. 289–300.
STOC-2004-ChekuriGKK #multi #scheduling: Multi-processor scheduling to minimize flow time with epsilon resource augmentation (CC, AG, SK, AK), pp. 363–372.
ICPR-v3-2004-HanJ #fault tolerance #image #parallel: From Massively Parallel Image Processors to Fault-Tolerant Nanocomputers (JH, PJ), pp. 2–7.
SAC-2004-UhrigU #fine-grained #parallel #power management #thread: Fine-grained power management for multithreaded processor cores (SU, TU), pp. 907–908.
ASPLOS-2004-EkanayakeKM #network #power management: An ultra low-power processor for sensor networks (VNE, CKI, RM), pp. 27–36.
ASPLOS-2004-WangCWKGCYSMS #framework #multi #thread: Helper threads via virtual multithreading on an experimental itanium® 2 processor-based platform (PHW, JDC, HW, DK, BG, KMC, ABY, TS, SFM, JPS), pp. 144–155.
CC-2004-OzerNG #approximate #probability #using: Stochastic Bit-Width Approximation Using Extreme Value Theory for Customizable Processors (EÖ, AN, DG), pp. 250–264.
CGO-2004-KimLWCTZWYGS #physics #thread: Physical Experimentation with Prefetching Helper Threads on Intel’s Hyper-Threaded Processors (DK, SWL, PHW, JdC, XT, XZ, HW, DY, MG, JPS), pp. 27–38.
CGO-2004-KudlurFCRCM #heuristic #named #scheduling: FLASH: Foresighted Latency-Aware Scheduling Heuristic for Processors with Customized Datapaths (MK, KF, MLC, RAR, NC, SAM), pp. 201–212.
CGO-2004-Winkel #performance #scheduling: Exploring the Performance Potential of Itanium® Processors with ILP-based Scheduling (SW), pp. 189–200.
HPCA-2004-CristalOLV #commit: Out-of-Order Commit Processors (AC, DO, JL, MV), pp. 48–59.
HPCA-2004-FalconRV #multi #thread: A Low-Complexity, High-Performance Fetch Unit for Simultaneous Multithreading Processors (AF, AR, MV), pp. 244–253.
HPCA-2004-KalogeropulosRRST: Processor Aware Anticipatory Prefetching in Loops (SK, MR, VR, YS, PT), pp. 106–117.
HPCA-2004-Michaud #capacity #execution #manycore #migration: Exploiting the Cache Capacity of a Single-Chip Multi-Core Processor with Execution Migration (PM), pp. 186–197.
LCTES-2004-DaveauTLS #embedded #framework: A retargetable register allocation framework for embedded processors (JMD, TT, TL, MS), pp. 202–210.
LCTES-2004-ZhuangP #embedded #power management: Power-efficient prefetching via bit-differential offset assignment on embedded processors (XZ, SP), pp. 67–77.
LCTES-2004-ZhuangZP #embedded: Hardware-managed register allocation for embedded processors (XZ, TZ, SP), pp. 192–201.
DAC-2003-ChenRRD #programmable #scalability #self: A scalable software-based self-test methodology for programmable processors (LC, SR, AR, SD), pp. 548–553.
DAC-2003-DescampsBGIP #design #network #using: Design of a 17-million gate network processor using a design factory (GED, SB, SG, SI, AP), pp. 844–849.
DAC-2003-Kumar #design: Interconnect and noise immunity design for the Pentium 4 processor (RK0), pp. 938–943.
DAC-2003-KwonK: Optimal voltage allocation techniques for dynamically variable voltage processors (WCK, TK), pp. 125–130.
DAC-2003-NohlGBALSM #architecture #encoding #modelling #synthesis #using: Instruction encoding synthesis for architecture exploration using hierarchical processor models (AN, VG, GB, AH, RL, OS, HM), pp. 262–267.
DAC-2003-StinsonR #generative: A 1.5GHz third generation itanium® 2 processor (JS, SR), pp. 706–709.
DATE-2003-BeeckGBMCD #data transformation #implementation #power management #realtime: Background Data Organisation for the Low-Power Implementation in Real-Time of a Digital Audio Broadcast Receiver on a SIMD Processor (POdB, CG, EB, MM, FC, GD), pp. 11144–11145.
DATE-2003-BraunWSLMN #abstraction #memory management #multi: Processor/Memory Co-Exploration on Multiple Abstraction Levels (GB, AW, OS, RL, HM, AN), pp. 10966–10973.
DATE-2003-ChangKWH #named: G-MAC: An Application-Specific MAC/Co-Processor Synthesizer (ACYC, WAK, ACHW, TH), pp. 11134–11135.
DATE-2003-Dales #configuration management: Managing a Reconfigurable Processor in a General Purpose Workstation Environment (MD), pp. 10980–10985.
DATE-2003-FeiRRJ #energy #estimation: Energy Estimation for Extensible Processors (YF, SR, AR, NKJ), pp. 10682–10687.
DATE-2003-GriesKSK #case study #modelling #network #simulation: Comparing Analytical Modeling with Simulation for Network Processors: A Case Study (MG, CK, CS, KK), pp. 20256–20261.
DATE-2003-KranitisXGPZ #low cost #self: Low-Cost Software-Based Self-Testing of RISC Processor Cores (NK, GX, DG, AMP, YZ), pp. 10714–10719.
DATE-2003-LiliusTV #architecture #evaluation #performance #protocol: Fast Evaluation of Protocol Processor Architectures for IPv6 Routing (JL, DT, SV), pp. 20158–20163.
DATE-2003-LuoPJ #communication #distributed #embedded #realtime #scalability: Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems (JL, LSP, NKJ), pp. 11150–11151.
DATE-2003-LykakisMVNPSKPR #performance #protocol: Efficient Field Processing Cores in an Innovative Protocol Processor System-on-Chip (GL, NM, KV, NAN, SP, GS, GEK, DNP, DIR), pp. 20014–20019.
DATE-2003-MaciiMCZ #algorithm #embedded #energy: A New Algorithm for Energy-Driven Data Compression in VLIW Embedded Processors (AM, EM, FC, RZ), pp. 10024–10029.
DATE-2003-MarchalGPBBCC #energy #memory management #multi: SDRAM-Energy-Aware Memory Allocation for Dynamic Multi-Media Applications on Multi-Processor Platforms (PM, JIG, LP, DB, LB, FC, HC), pp. 10516–10523.
DATE-2003-MazzeoRSM #implementation: FPGA-Based Implementation of a Serial RSA Processor (AM, LR, GPS, NM), pp. 10582–10589.
DATE-2003-NicolaescuVN #embedded #power management: Reducing Power Consumption for High-Associativity Data Caches in Embedded Processors (DN, AVV, AN), pp. 11064–11069.
DATE-2003-RosaLP #configuration management #design #hardware: Hardware/Software Design Space Exploration for a Reconfigurable Processor (ALR, LL, CP), pp. 10570–10575.
SIGMOD-2003-MaddenFHH #design #network #query: The Design of an Acquisitional Query Processor For Sensor Networks (SM, MJF, JMH, WH), pp. 491–502.
VLDB-2003-FlorescuHKLRWCSA #streaming #xquery: The BEA/XQRL Streaming XQuery Processor (DF, CH, DK, PL, FR, TW, MJC, AS, GA), pp. 997–1008.
TACAS-2003-BarayCDM #functional #generative #testing #validation: Code-Based Test Generation for Validation of Functional Processor Descriptions (FB, PC, DD, HM), pp. 569–584.
PLDI-2003-ChuFM #clustering #multi: Region-based hierarchical operation partitioning for multicluster processors (MLC, KF, SAM), pp. 300–311.
PLDI-2003-GeorgeB #network: Taming the IXP network processor (LG, MB), pp. 26–37.
SAC-2003-CornoCRS #automation #generative #pipes and filters: Automatic Test Program Generation for Pipeline Processors (FC, GC, MSR, GS), pp. 736–740.
CGO-2003-CollardL #optimisation: Optimizations to Prevent Cache Penalties for the Intel ® Itanium 2 Processor (JFC, DML), pp. 105–114.
CGO-2003-GibertSG #clustering #distributed #memory management #scheduling: Local Scheduling Techniques for Memory Coherence in a Clustered VLIW Processor with a Distributed Data Cache (EG, FJS, AG), pp. 193–203.
HPCA-2003-El-MoursyA #performance #policy #smt: Front-End Policies for Improved Issue Efficiency in SMT Processors (AEM, DHA), pp. 31–40.
HPCA-2003-JosephBM #performance: Control Techniques to Eliminate Voltage Emergencies in High Performance Processors (RJ, DMB, MM), pp. 79–90.
HPCA-2003-KhailanyDRKOT #scalability: Exploring the VLSI Scalability of Stream Processors (BK, WJD, SR, UJK, JDO, BT), pp. 153–164.
HPCA-2003-MutluSWP #execution #scalability: Runahead Execution: An Alternative to Very Large Instruction Windows for Out-of-Order Processors (OM, JS, CW, YNP), pp. 129–140.
HPCA-2003-RedstoneEL #named #smt #thread: Mini-Threads: Increasing TLP on Small-Scale SMT Processors (JR, SJE, HML), pp. 19–30.
HPCA-2003-TerechkoTGEC #clustering #communication #modelling: Inter-Cluster Communication Models for Clustered VLIW Processors (AT, ELT, MG, JTJvE, HC), pp. 354–364.
HPDC-2003-BucurE #clustering #multi #policy #simulation: Trace-Based Simulations of Processor Co-Allocation Policies in Multiclusters (AIDB, DHJE), pp. 70–79.
LCTES-2003-ZhuangLP #embedded #optimisation: Storage assignment optimizations through variable coalescence for embedded processors (XZ, CL, SP), pp. 220–231.
PPoPP-2003-McDowellEG #parallel #thread: Improving server software support for simultaneous multithreaded processors (LM, SJE, SDG), pp. 37–48.
DAC-2002-BonaSSZSZ #clustering #embedded #energy #estimation #optimisation: Energy estimation and optimization of embedded VLIW processors based on instruction clustering (AB, MS, DS, VZ, CS, RZ), pp. 886–891.
DAC-2002-ChenD: Software-based diagnosis for processors (LC, SD), pp. 259–262.
DAC-2002-SchaumontKV #design: Unlocking the design secrets of a 2.29 Gb/s Rijndael processor (PS, HK, IV), pp. 634–639.
DAC-2002-SemeriaMPESN #concurrent #design #multi #thread #verification: RTL c-based methodology for designing and verifying a multi-threaded processor (LS, RM, BMP, AE, AS, DN), pp. 123–128.
DAC-2002-Ykman-CouvreurLVCNK #memory management #network #optimisation #performance: System-level performance optimization of the data queueing memory management in high-speed network processors (CYC, JL, DV, FC, AN, GEK), pp. 518–523.
DATE-2002-BeniniBMM #embedded #energy: Hardware-Assisted Data Compression for Energy Minimization in Systems with Embedded Processors (LB, DB, AM, EM), pp. 449–453.
DATE-2002-KranitisPGZ #effectiveness #self: Effective Software Self-Test Methodology for Processor Cores (NK, AMP, DG, YZ), pp. 592–597.
DATE-2002-PetrovO #embedded #performance: Power Efficient Embedded Processor Ip’s through Application-Specific Tag Compression in Data Caches (PP, AO), pp. 1065–1071.
DATE-2002-Phillips #embedded #how: How to Choose Semiconductor IP? — Embedded Processor (IP), p. 14.
DATE-2002-PozziVI #automation #embedded #identification: Automatic Topology-Based Identification of Instruction-Set Extensions for Embedded Processors (LP, MV, PI), p. 1138.
DATE-2002-QuanH #energy #scheduling: Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor (GQ, XH), pp. 782–787.
DATE-2002-TangGN #embedded #power management: Power Savings in Embedded Processors through Decode Filer Cache (WT, RKG, AN), pp. 443–448.
VLDB-2002-LudascherMP #query #transducer #xml: A Transducer-Based XML Query Processor (BL, PM, YP), pp. 227–238.
AdaEurope-2002-ChatzigeorgiouS #embedded #object-oriented #performance #power of #programming: Evaluating Performance and Power of Object-Oriented Vs. Procedural Programming in Embedded Processors (AC, GS), pp. 65–75.
ICPR-v1-2002-Baggenstoss #classification: The Chain-Rule Processor: Optimal Classification Through Signal Processing (PMB), pp. 230–234.
SAC-2002-JeeP #evaluation #performance: Performance evaluation for a compressed-VLIW processor (SJ, KP), pp. 913–917.
CC-2002-RelePOG #functional #optimisation: Optimizing Static Power Dissipation by Functional Units in Superscalar Processors (SR, SP, SÖ, RG), pp. 261–275.
HPCA-2002-SemeraroMBADS #design #energy #multi #scalability #using: Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling (GS, GM, RB, DHA, SD, MLS), pp. 29–42.
HPCA-2002-UnsalKKM #energy #framework: The Minimax Cache: An Energy-Efficient Framework for Media Processors (OSÜ, IK, CMK, CAM), pp. 131–140.
HPCA-2002-WangWCGKS #execution #memory management: Memory Latency-Tolerance Approaches for Itanium Processors: Out-of-Order Execution vs. Speculative Precomputation (PHW, HW, JDC, EG, RMK, JPS), pp. 187–196.
HPCA-2002-YangPFV #design #energy: Exploiting Choice in Resizable Cache Design to Optimize Deep-Submicron Processor Energy-Delay (SHY, MDP, BF, TNV), pp. 151–161.
HPDC-2002-BucurE #clustering #multi #performance: The Performance of Processor Co-Allocation in Multicluster Systems (AIDB, DHJE), p. 414.
LCTES-SCOPES-2002-MilnerD #performance #pipes and filters: Quick piping: a fast, high-level model for describing processor pipelines (CWM, JWD), pp. 175–184.
DAC-2001-ChenBD #embedded #fault #testing #using: Testing for Interconnect Crosstalk Defects Using On-Chip Embedded Processor Cores (LC, XB, SD), pp. 317–320.
DAC-2001-Gebotys #embedded #memory management: Utilizing Memory Bandwidth in DSP Embedded Processors (CHG), pp. 347–352.
DAC-2001-KarimNDR #architecture #communication #network: On-Chip Communication Architecture for OC-768 Network Processors (FK, AN, SD, RRR), pp. 678–683.
DAC-2001-LaiC #testing: Instruction-Level DFT for Testing Processor and IP Cores in System-on-a-Chip (WCL, KTC), pp. 59–64.
DAC-2001-PetrovO #architecture #embedded: Speeding Up Control-Dominated Applications through Microarchitectural Customizations in Embedded Processors (PP, AO), pp. 512–517.
DAC-2001-QuanH #energy #performance #realtime #scheduling: Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors (GQ, XH), pp. 828–833.
DAC-2001-UdayanarayananC #code generation: Address Code Generation for Digital Signal Processors (SU, CC), pp. 353–358.
DAC-2001-WangKMR #hardware #set: Hardware/Software Instruction Set Configurability for System-on-Chip Processors (AW, EK, DEM, CR), pp. 184–188.
DATE-2001-AkgulM #hardware: System-on-a-chip processor synchronization support in hardware (BSA, VJMI), pp. 633–641.
DATE-2001-BekooijEWB #behaviour #functional: Functional units with conditional input/output behavior in VLIW processors (MB, LJME, AvdW, NGB), p. 822.
DATE-2001-DielissenMBHSHW #power management: Power-efficient layered turbo decoder processor (JD, JLvM, MB, FH, SS, JH, AvdW), pp. 246–251.
DATE-2001-JungYC #analysis #multi #performance: Performance improvement of multi-processor systems cosimulation based on SW analysis (JJ, SY, KC), pp. 749–753.
DATE-2001-PaschalisGKPZ #embedded #self: Deterministic software-based self-testing of embedded processor cores (AMP, DG, NK, MP, YZ), pp. 92–96.
DATE-2001-PaulinKB #architecture #embedded #network #requirements #tool support: Network processors: a perspective on market requirements, processor architectures and embedded S/W tools (PGP, FK, PB), pp. 420–429.
DATE-2001-RoussellePBMV #embedded #fault: A register-transfer-level fault simulator for permanent and transient faults in embedded processors (CR, MP, AB, TM, HTV), p. 811.
DATE-2001-SamiSSZZ #embedded: Exploiting data forwarding to reduce the power budget of VLIW embedded processors (MS, DS, CS, VZ, RZ), pp. 252–257.
ICDAR-2001-LehalSL: A Shape Based Post Processor for Gurmukhi OCR (GSL, CS, RL), pp. 1105–1109.
PLDI-2001-SchnarrHL #compilation #named: Facile: A Language and Compiler for High-Performance Processor Simulators (ES, MDH, JRL), pp. 321–331.
SAC-2001-LeeYKP #algorithm #order #performance #towards: Processor reordering algorithms toward efficient GEN_BLOCK redistribution (SL, HGY, MSK, MSP), pp. 539–543.
HPCA-2001-CorbalEV #generative: DLP + TLP Processors for the Next Generation of Media Workloads (JC, RE, MV), pp. 219–228.
HPCA-2001-KailasEA #clustering #code generation #framework #named: CARS: A New Code Generation Framework for Clustered ILP Processors (KK, KE, AKA), pp. 133–143.
HPCA-2001-MichaudS #data flow #scalability: Data-Flow Prescheduling for Large Instruction Windows in Out-of-Order Processors (PM, AS), pp. 27–36.
HPCA-2001-ZillesS #profiling #programmable: A Programmable Co-Processor for Profiling (CBZ, GSS), pp. 241–252.
LCTES-OM-2001-CadotKLRS #communication #embedded #multi #named: ENSEMBLE: A Communication Layer for Embedded Multi-Processor Systems (SC, FK, KL, KvR, HJS), pp. 56–63.
LCTES-OM-2001-KimH #embedded #hybrid #power management #realtime #runtime #scalability: Hybrid Run-time Power Management Technique for Real-time Embedded System with Voltage Scalable Processor (MK, SH), pp. 11–19.
LCTES-OM-2001-LeeEMC #embedded #energy: An Accurate Instruction-Level Energy Consumption Model for Embedded RISC Processors (SL, AE, SLM, NC), pp. 1–10.
LCTES-OM-2001-WagnerL #c #compilation #design #industrial #network: C Compiler Design for an Industrial Network Processor (JW, RL), pp. 155–164.
SOSP-2001-SpalinkKPG #network #robust #using: Building a Robust Software-Based Router Using Network Processors (TS, SK, LLP, YG), pp. 216–229.
DAC-2000-ChenDSSC #embedded #hardware #self: Embedded hardware and software self-testing methodologies for processor cores (LC, SD, PS, KS, YC), pp. 625–630.
DAC-2000-GebotysGW #architecture #power management: Power minimization derived from architectural-usage of VLIW processors (CHG, RJG, SW), pp. 308–311.
DAC-2000-GoelL #verification: Formal verification of an IBM CoreConnect processor local bus arbiter core (AG, WRL), pp. 196–200.
DAC-2000-Puig-MedinaEK #configuration management #verification: Verification of configurable processor cores (MPM, GE, PK), pp. 426–431.
DATE-2000-CatthoorDK #architecture #compilation #data transfer #how #memory management #question: How to Solve the Current Memory Access and Data Transfer Bottlenecks: At the Processor Architecture or at the Compiler Level? (FC, NDD, CEK), pp. 426–433.
DATE-2000-GuptaGMC #analysis #program transformation #programmable: Analysis of High-Level Address Code Transformations for Programmable Processors (SG, RKG, MM, FC), pp. 9–13.
DATE-2000-HergenhanR #analysis #architecture #embedded: Static Timing Analysis of Embedded Software on Advanced Processor Architectures (AH, WR), pp. 552–559.
DATE-2000-IshiharaY #embedded #reduction: A Power Reduction Technique with Object Code Merging for Application Specific Embedded Processors (TI, HY), pp. 617–623.
DATE-2000-Leupers: Code Selection for Media Processors with SIMD Instructions (RL), pp. 4–8.
DATE-2000-PeesHM #using: Retargeting of Compiled Simulators for Digital Signal Processors Using a Machine Description Language (SP, AH, HM), pp. 669–673.
DATE-2000-YooLJRCC #execution #performance: Fast Hardware-Software Coverification by Optimistic Execution of Real Processor (SY, JeL, JJ, KR, YC, KC), pp. 663–668.
ICPR-v4-2000-StofflerBF #realtime #using: Real-Time Obstacle Avoidance Using an MPEG-Processor-Based Optic Flow Sensor (NOS, TB, GF), pp. 4161–4166.
ASPLOS-2000-SnavelyT #multi #thread: Symbiotic Jobscheduling for a Simultaneous Multithreading Processor (AS, DMT), pp. 234–244.
ASPLOS-2000-SundaramoorthyPR #fault tolerance #performance: Slipstream Processors: Improving both Performance and Fault Tolerance (KS, ZP, ER), pp. 257–268.
CC-2000-Kim #compilation #embedded #optimisation: Advanced Compiler Optimization for Calm RISC8 Low-End Embedded Processor (DHK), pp. 173–188.
CC-2000-WangTP #framework #memory management: A Framework for Loop Distribution on Limited On-Chip Memory Processors (LW, WT, SP), pp. 141–156.
HPCA-2000-ChiuehP #design #memory management #network: Cache Memory Design for Network Processors (TcC, PP), pp. 409–418.
HPCA-2000-LeeWY #predict: Decoupled Value Prediction on Trace Processors (SJL, YW, PCY), pp. 231–240.
HPCA-2000-MoshovosS #dependence #memory management #trade-off: Memory Dependence Speculation Tradeoffs in Centralized, Continuous-Window Superscalar Processors (AM, GSS), pp. 301–312.
HPCA-2000-TorrellasYN #effectiveness #integration #towards: Toward a Cost-Effective DSM Organization That Exploits Processor-Memory Integration (JT, LY, ATN), pp. 15–25.
HPDC-2000-HeissRN #clustering #distributed #scalability: Distributed Processor Allocation in Large PC Clusters (HUH, CAFDR, POAN), pp. 288–289.
ISMM-2000-PlakalF #concurrent #garbage collection #parallel #slicing #thread #using: Concurrent Garbage Collection Using Program Slices on Multithreaded Processors (MP, CNF), pp. 94–100.
LCTES-2000-BairagiPA #embedded #framework #quality #set: A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors (DB, SP, DPA), pp. 81–95.
LCTES-2000-ParkLLHK #embedded #performance: A Power Efficient Cache Structure for Embedded Processors Based on the Dual Cache Structure (GHP, KWL, JHL, TDH, SDK), pp. 162–177.
OSDI-2000-CorbalanML: Performance-Driven Processor Allocation (JC, XM, JL), pp. 59–73.
DAC-1999-AdarioRB #architecture #configuration management #image: Dynamically Reconfigurable Architecture for Image Processor Applications (AMSA, ELR, SB), pp. 623–628.
DAC-1999-AllenBS: Converting a 64b PowerPC Processor from CMOS Bulk to SOI Technology (DA, DB, BS), pp. 892–897.
DAC-1999-Fisher #embedded: Customized Instruction-Sets for Embedded Processors (JAF), pp. 253–257.
DAC-1999-GoodmanCD #design #embedded #encryption #implementation #scalability: Design and Implementation of a Scalable Encryption Processor with Embedded Variable DC/DC Converter (JG, AC, APD), pp. 855–860.
DAC-1999-TupuriKA #automation #constraints #functional #generative #testing #using: Test Generation for Gigahertz Processors Using an Automatic Functional Constraint Extractor (RST, AK, JAA), pp. 647–652.
DATE-1999-AlippiFPS #approach #configuration management #design: A DAG-Based Design Approach for Reconfigurable VLIW Processors (CA, WF, LP, MS), pp. 778–779.
DATE-1999-Leupers #code generation #embedded: Exploiting Conditional Instructions in Code Generation for Embedded VLIW Processors (RL), p. 105–?.
VLDB-1999-AilamakiDHW #question: DBMSs on a Modern Processor: Where Does Time Go? (AA, DJD, MDH, DAW), pp. 266–277.
ITiCSE-1999-FuenteCC #architecture #education: Teaching computer architecture with a new superscalar processor emulator (SRdlF, MIGC, RMC), pp. 99–102.
ICSM-1999-JohnstoneSW #assembly #compilation #experience: Experience Paper: Reverse Compilation of Digital Signal Processor Assembler Source to ANSI-C (AJ, ES, TW), pp. 316–325.
PLDI-1999-CooperM #embedded: Enhanced Code Compression for Embedded RISC Processors (KDC, NM), pp. 139–149.
CIKM-1999-AponWD #approach #learning #parallel: A Learning Approach to Processor Allocation in Parallel Systems (AWA, TDW, LWD), pp. 531–537.
SAC-1999-DunningR #estimation #heuristic #optimisation: A Heuristic Cost Estimation Method for Optimizing Assignment of Tasks to Processors (LAD, SR), pp. 358–364.
HPCA-1999-BrooksM #performance: Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance (DMB, MM), pp. 13–22.
HPCA-1999-DurbhakulaPA #multi #simulation #trade-off: Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors (MD, VSP, SVA), pp. 23–32.
HPCA-1999-HilyS #effectiveness #execution #multi #thread: Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading (SH, AS), pp. 64–67.
HPCA-1999-JacobsonS #preprocessor: Instruction Pre-Processing in Trace Processors (QJ, JES), pp. 125–129.
HPCA-1999-RotenbergJS #case study #independence: A Study of Control Independence in Superscalar Processors (ER, QJ, JES), pp. 115–124.
HPCA-1999-TullsenLEL #fine-grained #multi #thread: Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor (DMT, JLL, SJE, HML), pp. 54–58.
HPCA-1999-WallaceTC #multi: Instruction Recycling on a Multiple-Path Processor (SW, DMT, BC), pp. 44–53.
HPDC-1999-CoadyOF #clustering #embedded #memory management #network #using: Using Embedded Network Processors to Implement Global Memory Management in a Workstation Cluster (YC, JSO, MJF), pp. 319–328.
LCTES-1999-EcksteinK #low cost: Minimizing Cost of Local Variables Access for DSP-Processors (EE, AK), pp. 20–27.
LCTES-1999-SchneiderF #abstract interpretation #behaviour #pipes and filters #predict: Pipeline Behavior Prediction for Superscalar Processors by Abstract Interpretation (JS, CF), pp. 35–44.
CAV-1999-BaumgartnerHSA #abstraction #algorithm #model checking: Model Checking the IBM Gigahertz Processor: An Abstraction Algorithm for High-Performance Netlists (JB, TH, VS, AA), pp. 72–83.
CAV-1999-RameshB #case study #design #pipes and filters #tool support #using #validation: Validation of Pipelined Processor Designs Using Esterel Tools: A Case Study (SR, PB), pp. 84–95.
DAC-1998-HilgenstockHONP #multi #video: A Video Signal Processor for MIMD Multiprocessing (JH, KH, JO, DN, PP), pp. 50–55.
DAC-1998-KarkowskiC #algorithm #design #embedded #multi: Design Space Exploration Algorithm for Heterogeneous Multi-Processor Embedded System Design (IK, HC), pp. 82–87.
DAC-1998-LeeKPM #architecture #multi #programmable: Media Architecture: General Purpose vs. Multiple Application-Specific Programmable Processor (CL, JK, MP, WHMS), pp. 321–326.
DAC-1998-TaylorQBDHHR #functional #multi #verification: Functional Verification of a Multiple-issue, Out-of-Order, Superscalar Alpha Processor — The DEC Alpha 21264 Microprocessor (SAT, MQ, DB, ND, SH, JH, CR), pp. 638–643.
DATE-1998-FassnachtS #analysis #optimisation: Timing Analysis and Optimization of a High-Performance CMOS Processor Chipset (UF, JS), pp. 325–331.
DATE-1998-KoehlBLKP #design: A Flat, Timing-Driven Design System for a High-Performance CMOS Processor Chipset (JK, UB, TL, BK, TP), pp. 312–320.
DATE-1998-PandaDN #embedded: Data Cache Sizing for Embedded Processor Applications (PRP, NDD, AN), pp. 925–926.
DATE-1998-SalapuraG #co-evolution #design #fuzzy #hardware: Hardware/Software Co-Design of a Fuzzy RISC Processor (VS, MG), pp. 875–882.
DATE-1998-TomiyamaIIY #design #reduction #scheduling: Instruction Scheduling for Power Reduction in Processor-Based System Design (HT, TI, AI, HY), pp. 855–860.
DATE-1998-WahlV #performance #validation: A VHDL SGRAM Model for the Validation Environment of a High Performance Graphic Processor (MGW, HV), pp. 937–938.
TACAS-1998-Bryant #pipes and filters #verification: Formal Verification of Pipelined Processors (REB), pp. 1–4.
CSMR-1998-OhtaMI #on the #source code #verification: On Constructing a Tool to Verify Programs for Processors Built in Machines (TO, NM, YI), pp. 52–59.
ICPR-1998-StofflerS #detection #realtime: An MPEG-processor-based robot vision system for real-time detection of moving objects by a moving observer (NOS, ZS), pp. 477–481.
ECOOP-1998-VijaykrishnanRG #architecture #java #object-oriented: Object-Oriented Architectural Support for a Java Processor (NV, NR, RG), pp. 330–354.
SAC-1998-SimpsonS #approach #multi: A multiple processor approach to data compression (JLS, CLS), pp. 641–649.
ASPLOS-1998-FuJLC #performance #scheduling: Value Speculation Scheduling for High Performance Processors (CyF, MDJ, SYL, TMC), pp. 262–271.
ASPLOS-1998-RanganathanGAB #database #performance: Performance of Database Workloads on Shared-Memory Systems with Out-of-Order Processors (PR, KG, SVA, LAB), pp. 307–318.
ASPLOS-1998-SchnarrL #performance #simulation #using: Fast Out-Of-Order Processor Simulation Using Memoization (ES, JRL), pp. 283–294.
HPCA-1998-HavankiBC #scheduling: Treegion Scheduling for Wide Issue Processors (WAH, SB, TMC), pp. 266–276.
HPCA-1998-TsaiJNY #concurrent #parallel #performance #thread: Performance Study of a Concurrent Multithreaded Processor (JYT, ZJ, EN, PCY), pp. 24–35.
HPCA-1998-TubellaG #detection #parallel #thread: Control Speculation in Multithreaded Processors through Dynamic Loop Detection (JT, AG), pp. 14–23.
HPDC-1998-NieplochaFD: Distant I/O: One-Sided Access to Secondary Storage on Remote Processors (JN, ITF, HD), pp. 148–154.
CAV-1998-Camilleri #design #multi #proving #theorem proving: A Role for Theorem Proving in Multi-Processor Design (AJC), pp. 45–48.
CAV-1998-SawadaH #execution #precise #verification: Processor Verification with Precise Exeptions and Speculative Execution (JS, WAHJ), pp. 135–146.
DAC-1997-HartoogRRDDHK #generative #hardware #tool support: Generation of Software Tools from Processor Descriptions for Hardware/Software Codesign (MRH, JAR, PDR, SD, DDD, EAH, NK), pp. 303–306.
DAC-1997-KimKP #programmable #synthesis: Synthesis of Application Specific Programmable Processors (KK, RK, MP), pp. 353–358.
DAC-1997-LiemCSPJGLFB #case study #development #embedded #multi: Am Embedded System Case Study: The Firm Ware Development Environment for a Multimedia Audio Processor (CL, MC, MS, PGP, AAJ, JMG, JL, XF, LB), pp. 780–785.
DAC-1997-Marwedel #code generation: Code Generation for Core Processors (PM), pp. 232–237.
EDTC-1997-KarthikeyanN #architecture: An asynchronous architecture for digital signal processors (MRK, SKN), p. 615.
EDTC-1997-LeijtenMTJ #architecture #data-driven #multi #named: PROPHID: a data-driven multi-processor architecture for high-performance DSP (JAJL, JLvM, AHT, JAGJ), p. 611.
EDTC-1997-LeupersM #generative #modelling: Retargetable generation of code selectors from HDL processor models (RL, PM), pp. 140–144.
EDTC-1997-LiemPJ #design #embedded #named: ReCode: the design and re-design of the instruction codes for embedded instruction-set processors (CL, PGP, AAJ), p. 612.
EDTC-1997-PandaDN #embedded #memory management #performance: Efficient utilization of scratch-pad memory in embedded processor applications (PRP, NDD, AN), pp. 7–11.
EDTC-1997-SmeetsAEK #programmable #video: Delay management for programmable video signal processors (MLGS, EHLA, GE, EAdK), pp. 126–133.
TACAS-1997-EijkBEA #generative: The Term Processor Generator Kimwitu (PvE, AB, HE, HA), pp. 96–111.
CIKM-1997-MehrotraHK #multi: Dealing with Partial Failures in Multiple Processor Primary-Backup Systems (SM, KH, SMK), pp. 371–378.
SAC-1997-LiMII #communication: Booking heterogeneous processor resources to reduce communication overhead (DL, AM, YI, NI), pp. 354–360.
SAC-1997-Liu #algorithm #evaluation #execution #parallel #performance #query: Performance evaluation of processor allocation algorithms for parallel query execution (KHL), pp. 393–402.
SAC-1997-LiuLS #clustering #concurrent #multi #performance #thread: An efficient processor partitioning and thread mapping strategy for mesh-connected multiprocessor systems (HL, WML, YS), pp. 403–412.
HPCA-1997-BhandarkarD #performance: Performance Characterization of the Pentium(r) Pro Processor (DB, JJD), pp. 288–299.
HPCA-1997-JacobsonBSS #control flow #multi: Control Flow Speculation in Multiscalar Processors (QJ, SB, NS, JES), pp. 218–229.
HPCA-1997-NoonburgS #framework #modelling #performance #statistics: A Framework for Statistical Modeling of Superscalar Processor Performance (DBN, JPS), pp. 298–309.
HPCA-1997-WolfeFDF #design #video: Datapath Design for a VLIW Video Signal Processor (AW, JF, SD, ESTF), pp. 24–35.
HPDC-1997-Downey #parallel: A Parallel Workload Model and its Implications for Processor Allocation (ABD), pp. 112–123.
HPDC-1997-SiuS #design pattern #network #parallel #using: Design Patterns for Parallel Computing using a Network of Processors (SS, AS), pp. 293–304.
DAC-1996-CasaubieilhMBBPRBEMBB #functional #verification: Functional Verification Methodology of Chameleon Processor (FC, AM, MB, MB, FP, FR, MB, JE, GM, GB, CB), pp. 421–426.
DAC-1996-ErcanliP #scheduling #synthesis: A Register File and Scheduling Model for Application Specific Processor Synthesis (EE, CAP), pp. 35–40.
DAC-1996-PopescuM #design #verification: Innovative Verification Strategy Reduces Design Cycle Time for High-End Sparc Processor (VP, BM), pp. 311–314.
DAC-1996-SrivastavaP #approach #implementation #linear #optimisation #programmable: Power Optimization in Programmable Processors and ASIC Implementations of Linear Systems: Transformation-based Approach (MBS, MP), pp. 343–348.
PODS-1996-LevyRU #query #using: Answering Queries Using Limited External Processors (AYL, AR, JDU), pp. 227–237.
SIGMOD-1996-Agarwal #algorithm #sorting: A Super Scalar Sort Algorithm for RISC Processors (RCA), pp. 240–246.
VLDB-1996-RysNS #parallel #relational #transaction: Intra-Transaction Parallelism in the Mapping of an Object Model to a Relational Multi-Processor System (MR, MCN, HJS), pp. 460–471.
CHI-1996-PageJAA #word: User Customization of a Word Processor (SRP, TJJ, UA, CDA), pp. 340–346.
ICPR-1996-FerrariBG #array #classification: A VLSI array processor accelerator for k-NN classification (AF, MB, RG), pp. 723–727.
ICPR-1996-RanganathanBV #array #image #linear: A dynamic frequency linear array processor for image processing (NR, NB, NV), pp. 611–615.
ICPR-1996-YamashitaFO #array #interface #memory management #realtime: An integrated memory array processor with a synchronous-DRAM interface for real-time vision applications (NY, YF, SO), pp. 575–580.
SEKE-1996-GuilfoyleHSB #algorithm #implementation #knowledge base: Implementation of Selected Data/Knowledge-Base Algorithms on a Digital Optoelectronic Processor (PSG, JMH, RVS, PBB), pp. 571–576.
ASPLOS-1996-PaiRAH #consistency #evaluation #memory management #modelling: An Evaluation of Memory Consistency Models for Shared-Memory Systems with ILP Processors (VSP, PR, SVA, TH), pp. 12–23.
ASPLOS-1996-SaghirCL: Exploiting Dual Data-Memory Banks in Digital Signal Processors (MARS, PC, CGL), pp. 234–243.
HPCA-1996-FarkasJC #design: Register File Design Considerations in Dynamically Scheduled Processors (KIF, NPJ, PC), pp. 40–51.
HPCA-1996-IyengarTB #infinity #modelling: Representative Traces for Processor Models with Infinite Cache (VSI, LT, PB), pp. 62–72.
DAC-1995-AharonGLLMMMS #functional #generative #verification: Test Program Generation for Functional Verification of PowerPC Processors in IBM (AA, DG, ML, YL, YM, CM, MM, GS), pp. 279–285.
DAC-1995-Albrecht #concurrent #configuration management #design #simulation: Concurrent Design Methodology and Configuration Management of the SIEMENS EWSD — CCS7E Processor System Simulation (TWA), pp. 222–227.
DAC-1995-WalkerG #algorithm #distributed #execution #parallel #simulation: Asynchronous, Distributed Event Driven Simulation Algorithm for Execution of VHDL on Parallel Processors (PAW, SG), pp. 144–150.
ICDAR-v2-1995-KimLK #architecture #array #hardware #implementation #parallel #recognition: Parallel hardware implementation of handwritten character recognition system on wavefront array processor architecture (YJK, SWL, MWK), pp. 715–718.
ICDAR-v2-1995-RheeF #documentation: Intelligent document assistant processor for pen-based computing systems (PKR, TF), pp. 1065–1068.
ECOOP-1995-ArditiC #framework #object-oriented #verification: An Object-Oriented Framework for the Formal Verification of Processors (LA, HC), pp. 215–234.
ECOOP-1995-DriesenHV #pipes and filters: Message Dispatch on Pipelined Processors (KD, UH, JV), pp. 253–282.
SAC-1995-GandolfiGMR #configuration management #design #fuzzy: Design of a VLSI very high speed reconfigurable digital fuzzy processor (EG, AG, MM, MR), pp. 477–481.
SAC-1995-Purdom #implementation #memory management #parallel: Implementing a system on a shared memory parallel processor (REP), pp. 187–190.
HPCA-1995-FarkasJC #execution #how #multi #question: How Useful Are Non-Blocking Loads, Stream Buffers and Speculative Execution in Multiple Issue Processors? (KIF, NPJ, PC), pp. 78–89.
HPCA-1995-FiskeD #concurrent #parallel #scheduling #thread: Thread Prioritization: A Thread Scheduling Mechanism for Multiple-Context Parallel Processors (SF, WJD), pp. 210–221.
HPCA-1995-HurSFOK #array #design #fault #logic #parallel #simulation: Massively Parallel Array Processor for Logic, Fault, and Design Error Simulation (YH, SAS, ESF, GEO, SK), pp. 340–347.
HPCA-1995-KawanoKTA #architecture #parallel #thread: Fine-Grain Multi-Thread Processor Architecture for Massively Parallel Processing (TK, SK, RiT, MA), pp. 308–317.
HPCA-1995-Lee #memory management #order: Memory Access Reordering in Vector Processors (DLL), pp. 380–389.
HPCA-1995-LiC #parallel #thread: The Effects of STEF in Finely Parallel Multithreaded Processors (YL, WC), pp. 318–325.
HPCA-1995-Weiss #implementation #multi #queue: Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors (SW), pp. 14–21.
LCT-RTS-1995-NilsenR #analysis #execution #worst-case: Worst-Case Execution Time Analysis on Modern Processors (KDN, BR), pp. 20–30.
SOSP-1995-NiehL #multi #named: SMART: A Processor Scheduler for Multimedia Applications (JN, MSL), p. 233.
DAC-1994-Casavant #design #named #pipes and filters #programmable: MIST — A Design Aid for Programmable Pipelined Processors (AEC), pp. 532–536.
DAC-1994-TeraiGNSO #automation #concept #design #performance: Basic Concept of Cooperative Timing-driven Design Automation Technology for High-speed RISC Processor HARP-1 (HT, KG, YN, YS, YO), pp. 262–269.
EDAC-1994-CoulombP #fourier #pipes and filters: PLFP256 A Pipelined Fourier Processor (PC, FP), pp. 245–249.
EDAC-1994-SarmientoE #implementation: Implementation of a CORDIC Processor for CFFT Computation in Gallium Arsenide Technology (RS, KE), pp. 238–244.
SIGMOD-1994-KrollW: Distributing a Search Tree Among a Growing Number of Processors (BK, PW), pp. 265–276.
SAS-1994-HarcourtMC #scheduling #specification: From Processor Timing Specifications to Static Intruction Scheduling (EAH, JM, TAC), pp. 116–130.
SAC-1994-Rodriguez #architecture: A minimal TTL processor for architecture exploration (BJR), pp. 338–340.
SAC-1994-WarwickT #algorithm #problem #search-based #using: Using a genetic algorithm to tackle the processors configuration problem (TW, EPKT), pp. 217–221.
HPDC-1994-MoralesA #design #implementation #logic #protocol: Design of a Header Processor for the PSi Implementation of the Logical Link Control Protocol in LANs (FAM, HAA), pp. 270–277.
ICLP-1994-AraujoR #distributed #execution #independence #named #parallel #prolog: PDP: Prolog Distributed Processor for Independent AND/OR Parallel Execution of Prolog (LA, JJR), pp. 142–156.
DAC-1993-CloutierT #pipes and filters #set #synthesis: Synthesis of Pipelined Instruction Set Processors (RJC, DET), pp. 583–588.
SIGMOD-1993-FushimiK #database #hardware #named #pipes and filters: GREO: A Commercial Database Processor Based on A Pipelined Hardware Sorter (SF, MK), pp. 449–452.
SIGMOD-1993-LoCRY #on the #pipes and filters: On Optimal Processor Allocation to Support Pipelined Hash Joins (MLL, MSC, CVR, PSY), pp. 69–78.
FME-1993-Barrett #model checking: Model Checking in Practice — The T9000 Virtual Channel Processor (GB), pp. 129–147.
AdaEurope-1993-GlasgowN: Data Compatibility in a Heterogeneous Processor Environment (MJG, BDN), pp. 197–215.
DAC-1992-HuangD #compilation #pipes and filters #set #synthesis: High Level Synthesis of Pipelined Instruction Set Processors and Back-End Compilers (IJH, AMD), pp. 135–140.
STOC-1992-AjtaiM #algorithm #linear #programming: A Deterministic Poly(log log N)-Time N-Processor Algorithm for Linear Programming in Fixed Dimension (MA, NM), pp. 327–338.
AdaEurope-1992-Mangold #ada #multi #named #set: AMPATS — A Multi Processor Ada Tool Set (KM), pp. 300–311.
SEKE-1992-TaT #algorithm #layout: Layout Algorithms for DFD Processors (KPT, TCT), pp. 567–573.
ASPLOS-1992-HenryJ #interface: A Tightly-Coupled Processor-Network Interface (DSH, CFJ), pp. 111–122.
ASPLOS-1992-MahlkeCHRS #scheduling: Sentinel Scheduling for VLIW and Superscalar Processors (SAM, WYC, WmWH, BRR, MSS), pp. 238–247.
STOC-1991-AspnesHS #coordination #multi #network: Counting Networks and Multi-Processor Coordination (JA, MH, NS), pp. 348–358.
STOC-1991-CoffmanG #proving #scheduling: Proof of the 4/3 Conjecture for Preemptive vs. Nonpreemptive Two-Processor Scheduling (EGCJ, MRG), pp. 241–248.
ICALP-1991-JungSS #algorithm #constraints #parallel #precedence #scheduling: A Parallel Algorithm for Two Processors Precedence Constraint Scheduling (HJ, MJS, PGS), pp. 417–428.
ICALP-1991-RaviAK #approximate #graph #problem #scheduling: Ordering Problems Approximated: Single-Processor Scheduling and Interval Graph Completion (RR, AA, PNK), pp. 751–762.
ASPLOS-1991-LeeKB #float #performance: The Floating-Point Performance of a Superscalar SPARC Processor (RLL, AYK, FAB), pp. 28–37.
ASPLOS-1991-SohiF #memory management: High-Bandwidth Data Memory Systems for Superscalar Processors (GSS, MF), pp. 53–62.
PPoPP-1991-BakewellQW #concurrent #source code: Mapping Concurrent Programs to VLIW Processors (HB, DJQ, PYW), pp. 21–27.
SOSP-1991-VaswaniZ #memory management #multi #scheduling: The Implications of Cache Affinity on Processor Scheduling for Multiprogrammed, Shared Memory Multiprocessors (RV, JZ), pp. 26–40.
DAC-1990-BreternitzS #architecture #synthesis: Architecture Synthesis of High-Performance Application-Specific Processors (MBJ, JPS), pp. 542–548.
PLDI-1990-Nickerson #graph #multi: Graph Coloring Register Allocation for Processors with Multi-Register Operands (BRN), pp. 40–52.
SIGIR-1990-CringeanEMW #parallel #using: Parallel Text Searching in Serial Files Using a Processor Farm (JKC, RE, GAM, PW), pp. 429–453.
CC-1990-Kastens #compilation #parallel: Compilation for Instruction Parallel Processors (UK), pp. 26–41.
SEKE-1989-ChenC: Assignment of Objects in a Dual Processor System with Limited Objects (HLC, SKC), pp. 85–92.
ASPLOS-1989-Gupta #fuzzy: The Fuzzy Barrier: A Mechanism for High Speed Synchronization of Processors (RG), pp. 54–63.
ASPLOS-1989-Roos #ada #realtime: A Real-Time Support Processor for Ada Tasking (JR), pp. 162–171.
DAC-1988-BergstraesserGHW #architecture #named #synthesis #tool support: SMART: Tools and Methods for Synthesis of VLSI Chips with Processor Architecture (TB, JG, KH, SW), pp. 654–657.
DAC-1988-Razouk #modelling #petri net #pipes and filters: The Use of Petri Nets for Modeling Pipelined Processors (RRR), pp. 548–553.
DAC-1988-SaitohINKMHHK #logic #simulation #using: Logic Simulation System Using Simulation Processor (SP) (MS, KI, AN, MK, JM, HH, FH, NK), pp. 225–230.
ICSE-1988-BarbacciWW #programming: Programming at the Processor-Memory-Switch Level (MB, CBW, JMW), pp. 19–29.
ICSE-1988-MathurK #modelling: Modeling Mutation on a Vector Processor (APM, EWK), pp. 154–161.
PPEALS-1988-LeBlancSB #experience #parallel #programming #scalability: Large-Scale Parallel Programming: Experience with the BBN Butterfly Parallel Processor (TJL, MLS, CMB), pp. 161–172.
JICSCP-1988-AlkalajS88 #architecture #concurrent #prolog: An Architectural Model for a Flat Concurrent Prolog Processor (LA, EYS), pp. 1277–1297.
JICSCP-1988-ChuM88 #named: SWIFT: A New Symbolic Processor (DAC, FGM), pp. 1415–1427.
JICSCP-1988-KurosawaYAB88 #architecture #performance #prolog: Instruction Architecture for a High Performance Integrated Prolog Processor IPP (KiK, SY, SA, TB), pp. 1506–1530.
SIGIR-1987-RasmussenW #array #clustering #distributed #documentation #using: Non-Hierarchic Document Clustering Using the ICL Distributed Array Processor (EMR, PW), pp. 132–139.
ASPLOS-1987-AtkinsonM: The Dragon Processor (RRA, EMM), pp. 65–69.
ASPLOS-1987-Clark #performance #pipes and filters: Pipelining and Performance in the VAX 8800 Processor (DWC), pp. 173–177.
ASPLOS-1987-SmithDVKRFSL: The ZS-1 Central Processor (JES, GED, BDV, SDK, CMR, DLF, KRS, JL), pp. 199–204.
ICLP-1987-MulderT87 #comparison #performance #prolog: A Performance Comparison between PLM and a M68020 PROLOG Processor (HM, ET), pp. 59–73.
STOC-1986-Cleve #security: Limits on the Security of Coin Flips when Half the Processors Are Faulty (Extended Abstract) (RC), pp. 364–369.
STOC-1986-KosarajuA #array #simulation: Optimal Simulations between Mesh-Connected Arrays of Processors (Preliminary Version) (SRK, MJA), pp. 264–272.
LFP-1986-Scheevel #graph #named #reduction: NORMA: A Graph Reduction Processor (MS), pp. 212–219.
LFP-1986-SteenkisteH #lisp: LISP on a Reduced-Instruction-Set-Processor (PS, JLH), pp. 192–201.
OOPSLA-1986-LewisGFT #named #performance: Swamp: A Fast Processor for Smalltalk-80 (DML, DRG, RJF, BWT), pp. 131–139.
ICLP-1986-Robinson86 #memory management #pattern matching #prolog: A Prolog Processor Based on a Pattern Matching Memory Device (IR), pp. 172–179.
DAC-1985-OdawaraTO #data flow #diagrams: Diagrammatic function description of microprocessor and data-flow processor (GO, MT, IO), pp. 731–734.
STOC-1985-VaziraniV #problem #scheduling: The Two-Processor Scheduling Problem is in R-NC (UVV, VVV), pp. 11–21.
ICALP-1985-VarmanR #array #matrix #multi #on the #using: On Matrix Multiplication Using Array Processors (PJV, IVR), pp. 487–496.
DAC-1984-Marwedel #design #tool support: The mimola design system: Tools for the design of digital processors (PM), pp. 587–593.
VLDB-1984-Borr #approach #database #distributed #multi #robust: Robustness to Crash in a Distributed Database: A Non Shared-memory Multi-Processor Approach (AJB), pp. 445–453.
STOC-1984-Vitanyi #distributed: Distributed Elections in an Archimedean Ring of Processors (Preliminary Version) (PMBV), pp. 542–547.
SLP-1984-TickW84 #pipes and filters #prolog #towards: Towards a Pipelined Prolog Processor (ET, DHDW), pp. 29–40.
DAC-1983-ChyanB #algorithm #array: A placement algorithm for array processors (DJC, MAB), pp. 182–188.
DAC-1983-Tendolkar: Diagnosis of TCM failures in the IBM 3081 Processor complex (NNT), pp. 196–200.
VLDB-1983-SaccaW #clustering #database: Database Partitioning in a Cluster of Processors (DS, GW), pp. 242–247.
DAC-1982-LiuE #design: Design of a graphic processor for computer-aided drafting (CKL, CME), pp. 514–520.
DAC-1982-TraceyK #hardware: A hardware description language for processor based digital systems (JHT, KSK), pp. 330–337.
STOC-1982-AtallahK #array #graph #problem: Graph Problems on a Mesh-Connected Processor Array (Preliminary Version) (MJA, SRK), pp. 345–353.
STOC-1982-DolevS #algorithm #multi #polynomial: Polynomial Algorithms for Multiple Processor Agreement (DD, HRS), pp. 401–407.
ASPLOS-1982-JohnssonW #architecture #bibliography: An Overview of the Mesa Processor Architecture (RKJ, JDW), pp. 20–29.
ASPLOS-1982-McLearST #guidelines: Guidelines for Creating a Debuggable Processor (REM, DMS, ET), pp. 100–106.
ASPLOS-1982-Rymarczyk #guidelines #pipes and filters: Coding Guidelines for Pipelined Processors (JWR), pp. 12–19.
DAC-1981-BlankSC #algorithm #architecture #parallel: A parallel bit map processor architecture for DA algorithms (TB, MS, WMvC), pp. 837–845.
DAC-1980-DyerLMS #design #simulation: The use of graphics processors for circuit design simulation at GTE AE Labs (JD, AL, EJM, WDS), pp. 446–450.
SIGMOD-1980-BancilhonS #database #design #on the #relational: On Designing an I/O Processor for a Relational Data Base Machine (FB, MS), p. 93–?.
STOC-1980-Angluin #network: Local and Global Properties in Networks of Processors (Extended Abstract) (DA), pp. 82–93.
STOC-1980-Lloyd #constraints #scheduling: Critical Path Scheduling of Task Systems with Resource and Processor Constraints (Extended Abstract) (ELL), pp. 436–446.
DAC-1979-Barbacci #evaluation #set #simulation #specification #synthesis: Instruction set processor specifications for simulation, evaluation, and synthesis (MB), pp. 64–72.
DAC-1979-Zimmermann #design: The MIMOLA design system a computer aided digital processor design method (GZ), pp. 53–58.
VLDB-1979-LuqueRRB #concurrent #database: Database Concurrent Processor (EL, JJR, AR, AB), pp. 273–279.
VLDB-1978-HollaarR #information retrieval #research: Current Research Into Specialized Processors For Text Information Retrieval (LAH, DCR), pp. 270–279.
VLDB-1978-LeilichSZ #database: A Search Processor for Data Base Management Systems (HOL, GS, HCZ), pp. 280–287.
VLDB-1978-OzkarahanO #composition #database: Microprocessor Based Modular Database Processors (EAO, KO), pp. 300–311.
ICALP-1978-CremersH #using: Mutual Exclusion of N Processors Using an O(N)-Valued Message Variable (Extended Abstract) (ABC, TNH), pp. 165–176.
GG-1978-Savitch #graph: Graphs of Processors (WJS), pp. 418–425.
DAC-1977-Pfeuffer #generative: Computer aided test pattern generation for digital processors (KP), pp. 68–77.
VLDB-1977-LangNKF #architecture #database #scalability: An Architectural Extension for a Large Database System Incorporating a Processor for Disk Search (TL, EN, KK, EBF), pp. 204–210.
ICSE-1976-KerschbergOP #query #relational: A Synthetic English Query Language for a Relational Accociative Processor (LK, EAO, JESP), pp. 505–519.
DAC-1975-AllevaCGP #evaluation #implementation #simulation #source code: A simulation system for implementation and evaluation of diagnostic programs of a special-purpose telecommunication switching processor (IA, MGC, RG, FP), pp. 123–133.
SOSP-1975-BrundageB #source code: Computational Processor Demands of Algol-60 Programs (REB, APB), pp. 161–168.
DAC-1974-DruffelSW #automation #design #performance: A simple, efficient design automation processor (LED, DCS, RAW), pp. 127–136.
DAC-1973-French: A Partitioned Ring Structure Processor (LJF), pp. 79–86.
DAC-1972-ChangDE #analysis #fault #logic #self #simulation: Logic simulation and fault analysis of a self-checking switching processor (HYC, RCD, RAE), pp. 128–137.
DAC-1972-IraniM #design: Optimal design of central processor data paths (KBI, GAM), pp. 341–349.
SOSP-1971-Baskett #dependence #scheduling: The Dependence of Computer System Queues upon Processing Time Distribution and Central Processor Scheduling (FB), pp. 109–113.
STOC-1970-Lindstrom #design #incremental #parsing: The Design of Parsers for Incremental Language Processors (GL), pp. 81–91.
STOC-1969-Korenjak #lr #performance: Efficient LR(1) Processor Construction (AJK), pp. 191–200.
STOC-1969-Rose #product line: Abstract Families of Processors (GFR), pp. 9–14.
DAC-1968-Darringer: A language for the description of digital computer processors (JAD).
SHARE-1965-SmithH #design #named: Autodraft: A language and processor for design and drafting (ODS, HRH).
SHARE-1964-Maier #geometry #named: AUTOLOFT: The AUTOLOFT geometric processor (RSM).