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Travelled to:
1 × USA
Collaborated with:
M.Dagenais N.C.Rumin
Talks about:
transistor (1) worst (1) group (1) estim (1) delay (1) case (1)

Person: Serge Gaiotti

DBLP DBLP: Gaiotti:Serge

Contributed to:

DAC 19891989

Wrote 1 papers:

DAC-1989-GaiottiDR #estimation #worst-case
Worst-case Delay Estimation of Transistor Groups (SG, MD, NCR), pp. 491–495.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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