Stem transistor$ (all stems)

87 papers:

DAC-2015-ChenSC #flexibility

A SPICE model of flexible transition metal dichalcogenide field-effect transistors (YYC, ZS, DC), p. 6.

DAC-2015-RakshitWLGM #design #power management #robust

Monolayer transition metal dichalcogenide and black phosphorus transistors for low power robust SRAM design (JR, RW, KTL, JG, KM), p. 6.

DATE-2015-LuLJLHCL #standard

Simultaneous transistor pairing and placement for CMOS standard cells (AL, HJL, EJJ, YPL, CHH, CCC, RBL), pp. 1647–1652.

DATE-2015-SedighiPHNN

A CNN-inspired mixed signal processor based on tunnel transistors (BS, IP, XSH, JN, MTN), pp. 1150–1155.

DAC-2014-DengBZW #performance

An Efficient Two-level DC Operating Points Finder for Transistor Circuits (JD, KB, YZ, NW), p. 6.

DAC-2014-YuSHEAB #metric #parametricity #using

Remembrance of Transistors Past: Compact Model Parameter Extraction Using Bayesian Inference and Incomplete New Measurements (LY, SS, CH, IAME, DAA, DSB), p. 6.

DATE-2014-ChenCH #array #configuration management #constraints #synthesis

Area minimization synthesis for reconfigurable single-electron transistor arrays with fabrication constraints (YHC, JYC, JDH), pp. 1–4.

DATE-2014-LiuCHWCDN #array #synthesis

Width minimization in the Single-Electron Transistor array synthesis (CWL, CEC, CYH, CYW, YCC, SD, VN), pp. 1–4.

DATE-2014-PalitSHHNN #architecture #case study

Impact of steep-slope transistors on non-von Neumann architectures: CNN case study (IP, BS, AH, XSH, JN, MTN), pp. 1–6.

DATE-2014-ZschieschangRKTZLBRBXMK #flexibility

Low-voltage organic transistors for flexible electronics (UZ, RR, UK, KT, TZ, FL, JB, HR, JNB, WX, BM, HK), pp. 1–6.

DAC-2013-GaillardonMABSLM #towards #using

Towards structured ASICs using polarity-tunable Si nanowire transistors (PEG, MDM, LGA, SB, DS, YL, GDM), p. 4.

DAC-2013-LeeLL #3d

Power benefit study for ultra-high density transistor-level monolithic 3D ICs (YJL, DBL, SKL), p. 10.

DAC-2013-SekitaniYTSS #using

Electrical artificial skin using ultraflexible organic transistor (TS, TY, MT, TS, TS), p. 3.

DATE-2013-ChenRSIFC #analysis #process

A SPICE-compatible model of graphene nano-ribbon field-effect transistors enabling circuit-level delay and power analysis under process variation (YYC, AR, AS, GI, GF, DC), pp. 1789–1794.

DATE-2013-ChiangTWHCDN #array #configuration management #on the #order #synthesis #using

On reconfigurable single-electron transistor arrays synthesis using reordering techniques (CEC, LFT, CYW, CYH, YCC, SD, VN), pp. 1807–1812.

DAC-2012-BobbaMLM #physics #synthesis

Physical synthesis onto a Sea-of-Tiles with double-gate silicon nanowire transistors (SB, MDM, YL, GDM), pp. 42–47.

DATE-2012-RudolfTWW #automation #configuration management #identification

Automated critical device identification for configurable analogue transistors (RR, PT, RW, PRW), pp. 858–861.

DATE-2012-TangZBM #analysis #correlation #modelling #statistics

Transistor-level gate model based statistical timing analysis considering correlations (QT, AZ, MB, NvdM), pp. 917–922.

DAC-2011-ChenEWDXN #array #automation #configuration management

Automated mapping for reconfigurable single-electron transistor arrays (YCC, SE, CYW, SD, YX, VN), pp. 878–883.

DAC-2011-Hu #how #why

New sub-20nm transistors: why and how (CH), pp. 460–463.

DAC-2011-ZhengSXHBC #array #framework #programmable

Programmable analog device array (PANDA): a platform for transistor-level analog reconfigurability (RZ, JS, CX, NH, BB, YC), pp. 322–327.

DAC-2011-ZukoskiYM #logic

Universal logic modules based on double-gate carbon nanotube transistors (AZ, XY, KM), pp. 884–889.

DATE-2011-YangM #design #robust

Robust 6T Si tunneling transistor SRAM design (XY, KM), pp. 740–745.

DAC-2010-BeeceXVZL #parametricity

Transistor sizing of custom high-performance digital circuits with parametric yield considerations (DKB, JX, CV, VZ, YL), pp. 781–786.

DAC-2010-TangZBM #analysis #simulation #statistics

RDE-based transistor-level gate simulation for statistical static timing analysis (QT, AZ, MB, NvdM), pp. 787–792.

DATE-2010-HenryN #power management

From transistors to MEMS: Throughput-aware power gating in CMOS circuits (MBH, LN), pp. 130–135.

DATE-2010-PanYZS #approach #megamodelling #order #performance #reduction

An efficient transistor-level piecewise-linear macromodeling approach for model order reduction of nonlinear circuits (XP, FY, XZ, YS), pp. 1673–1676.

DAC-2009-XuCWZ

Improving STT MRAM storage density through smaller-than-worst-case transistor sizing (WX, YC, XW, TZ), pp. 87–90.

DATE-2009-KhanK #adaptation #architecture #self

A self-adaptive system architecture to address transistor aging (OK, SK), pp. 81–86.

DATE-2009-MitraZPW #logic #using

Imperfection-immune VLSI logic circuits using Carbon Nanotube Field Effect Transistors (SM, JZ, NP, HW), pp. 436–441.

DATE-2009-PengC #parallel #simulation

Parallel transistor level full-chip circuit simulation (HP, CKC), pp. 304–307.

DAC-2008-KuonR #architecture #automation

Automated transistor sizing for FPGA architecture exploration (IK, JR), pp. 792–795.

DAC-2008-RajaVBG #analysis #modelling #performance

Transistor level gate modeling for accurate and fast timing, noise, and power analysis (SR, FV, MRB, JG), pp. 456–461.

DATE-2008-BacinschiMKG #adaptation #bias

An Analog On-Chip Adaptive Body Bias Calibration for Reducing Mismatches in Transistor Pairs (PBB, TM, KK, MG), pp. 698–703.

DATE-2008-BinkleyGGR #design

From Transistor to PLL — Analogue Design and EDA Methods (DB, HEG, GGEG, JSR).

DATE-2008-ClineCBTS #modelling

Transistor-Specific Delay Modeling for SSTA (BC, KC, DB, AT, SS), pp. 592–597.

DATE-2008-PakbazniaP #using

Coarse-Grain MTCMOS Sleep Transistor Sizing Using Delay Budgeting (EP, MP), pp. 385–390.

DAC-2007-ChiouJCC #algorithm #fine-grained #power management

Fine-Grained Sleep Transistor Sizing Algorithm for Leakage Power Minimization (DSC, DCJ, YTC, SCC), pp. 81–86.

DAC-2007-ZhuGSDK #architecture #power management #towards #using

Towards An Ultra-Low-Power Architecture Using Single-Electron Tunneling Transistors (CZ, Z(G, LS, RPD, RGK), pp. 312–317.

DATE-2007-AggarwalO #modelling #parametricity #reuse

Simulation-based reusable posynomial models for MOS transistor parameters (VA, UMO), pp. 69–74.

DATE-2007-ChenZLC #analysis #performance #statistics

Fast statistical circuit analysis with finite-point based transistor model (MC, WZ, FL, YC), pp. 1391–1396.

DATE-2007-SathanurCBMMP #bound #clustering #interactive #performance

Interactive presentation: Efficient computation of discharge current upper bounds for clustered sleep transistor sizing (AVS, AC, LB, AM, EM, MP), pp. 1544–1549.

DAC-2006-DupenloupLM #abstraction #functional #verification

Transistor abstraction for the functional verification of FPGAs (GD, TL, RM), pp. 1069–1072.

DAC-2006-ShiH #challenge #design #implementation #power management

Challenges in sleep transistor design and implementation in low-power designs (KS, DH), pp. 113–116.

DAC-2003-LongH #distributed #network #reduction

Distributed sleep transistor network for power reduction (CL, LH), pp. 181–186.

DATE-2003-GirardiB #automation #generative #layout #named

LIT — An Automatic Layout Generation Tool for Trapezoidal Association of Transistors for Basic Analog Building Blocks (AG, SB), pp. 11106–11107.

DATE-2003-WangZ #analysis #polynomial

Transistor-Level Static Timing Analysis by Piecewise Quadratic Waveform Matching (ZW, JZ), pp. 11026–11031.

HPCA-2003-Bhandarkar #enterprise

Billion Transistor Chips in Mainstream Enterprise Platforms of the Future (DB), p. 3.

DAC-2002-MartelDAWA #logic

Carbon nanotube field-effect transistors and logic circuits (RM, VD, JA, SJW, PA), pp. 94–98.

DATE-2002-DingM #performance

Optimal Transistor Tapering for High-Speed CMOS Circuits (LD, PM), pp. 708–713.

DAC-2000-KetkarKS #modelling

Convex delay models for transistor sizing (MK, KK, SSS), pp. 655–660.

DAC-2000-SundararajanSP #named

MINFLOTRANSIT: min-cost flow based transistor sizing tool (VS, SSS, KKP), pp. 649–664.

DAC-2000-YouVMX #approach #design #multi

A practical approach to parasitic extraction for design of multimillion-transistor integrated circuits (EY, LV, JM, WX), pp. 69–74.

DATE-2000-FrohlichGF #clustering #parallel #simulation

A New Partitioning Method for Parallel Simulation of VLSI Circuits on Transistor Level (NF, VG, JF), pp. 679–684.

DATE-2000-SchollB #generative #logic #multi #on the

On the Generation of Multiplexer Circuits for Pass Transistor Logic (CS, BB), pp. 372–378.

DAC-1999-JohnsonSR #performance

Leakage Control with Efficient Use of Transistor Stacks in Single Threshold CMOS (MCJ, DS, KR), pp. 442–445.

DAC-1999-MoussaSSDPCGJ #behaviour #design

Comparing RTL and Behavioral Design Methodologies in the Case of a 2M-Transistor ATM Shaper (IM, ZS, RS, MDN, MP, SC, LG, AAJ), pp. 598–603.

DATE-1999-ChoiB #array #design

OTA Amplifiers Design on Digital Sea-of-Transistors Array (JHC, SB), pp. 776–777.

DAC-1998-DartuP #analysis #named

TETA: Transistor-Level Engine for Timing Analysis (FD, LTP), pp. 595–598.

DATE-1998-ChatzigeorgiouN #effectiveness

Collapsing the Transistor Chain to an Effective Single Equivalent Transistor (AC, SN), pp. 2–6.

DAC-1997-KaoCA #multi

Transistor Sizing Issues and Tool For Multi-Threshold CMOS Technology (JK, AC, DA), pp. 409–414.

DAC-1997-KimK #algorithm #design #layout #performance

An Efficient Transistor Folding Algorithm for Row-Based CMOS Layout Design (JK, SMK), pp. 456–459.

DAC-1996-BasaranR #algorithm #constraints #performance

An O(n) Algorithm for Transistor Stacking with Performance Constraints (BB, RAR), pp. 221–226.

DAC-1996-DasguptaK96a #order #reliability

Hot-Carrier Reliability Enhancement via Input Reordering and Transistor Sizing (AD, RK), pp. 819–824.

FPLE-1995-ODonnell #architecture #education #functional #specification

From Transistors to Computer Architecture: Teaching Functional Circuit Specification in Hydra (JJO), pp. 195–214.

DAC-1994-KuehlmannCSL #fault #verification

Error Diagnosis for Transistor-Level Verification (AK, DIC, AS, DPL), pp. 218–224.

DAC-1994-MehrotraFL #approach #optimisation #probability

Stochastic Optimization Approach to Transistor Sizing for CMOS VLSI Circuits (SM, PDF, WL), pp. 36–40.

EDAC-1994-LinCHH #design

Cell Height Driven Transistor Sizing in a Cell Based Module Design (HRL, CLC, YCH, TH), pp. 425–429.

SAC-1994-Li #equivalence #graph #on the

On the equivalence of pull-up transistor assignment in PLA folding and distribution graph (WNL), pp. 374–378.

DAC-1993-CarlsonC #order #performance

Performance Enhancement of CMOS VLSI Circuits by Transistor Reordering (BSC, CYRC), pp. 361–366.

DAC-1991-HoS #flexibility #matrix

Flexible Transistor Matrix (FTM) (KCH, SS), pp. 475–480.

DAC-1990-SinghC #layout #matrix #order

A Transistor Reordering Technique for Gate Matrix Layout (US, CYRC), pp. 462–467.

DAC-1989-GaiottiDR #estimation #worst-case

Worst-case Delay Estimation of Transistor Groups (SG, MD, NCR), pp. 491–495.

DAC-1989-Marple #layout #optimisation

Transistor Size Optimization in the Tailor Layout System (DM), pp. 43–48.

DAC-1988-Boehner #automation #logic #named

LOGEX — an Automatic Logic Extractor Form Transistor to Gate Level for CMOS Technology (MB), pp. 517–522.

DAC-1987-Cirit

Transistor Sizing in CMOS Circuits (MAC), pp. 121–124.

DAC-1987-Hedlund #automation #named

Aesop: A Tool for Automated Transistor Sizing (KSH), pp. 114–120.

DAC-1987-LueM #game studies #layout #named

PLAY: Pattern-Based Symbolic Cell Layout: Part I: Transistor Placement (WJL, LPM), pp. 659–665.

DAC-1987-LursinsapG

Improving a PLA Area by Pull-Up Transistor Folding (CL, DG), pp. 608–614.

DAC-1986-ShihA #generative #physics #testing

Transistor-level test generation for physical failures in CMOS circuits (HCS, JAA), pp. 243–249.

DAC-1985-KaoFL #algorithm #automation

Algorithms for automatic transistor sizing in CMOS digital circuits (WHK, NF, CHL), pp. 781–784.

DAC-1985-ReddyRA #generative #testing

Transistor level test generation for MOS circuits (MKR, SMR, PA), pp. 825–828.

DAC-1985-Schaefer

A transistor-level logic-with-timing simulator for MOS circuits (TJS), pp. 762–765.

DAC-1983-BarzilaiHSTW #logic #simulation #using

Simulating pass transistor circuits using logic simulation machines (ZB, LMH, GMS, DTT, LSW), pp. 157–163.

DAC-1980-CoxC #array #automation #standard

The Standard Transistor Array (star) (Part II automatic cell placement techniques) (GWC, BDC), pp. 451–457.

DAC-1980-GouldE #array #design #standard

The standard transistor array (STAR): Part I A two-layer metal semicustom design system (JMG, TME), pp. 108–113.

DAC-1976-DobesB #automation #design #geometry #recognition

The automatic recognition of silicon gate transistor geometries: An LSI design aid program (ID, RB), pp. 327–335.