Travelled to:2 × USA
Collaborated with:M.Dagenais S.Gaiotti V.K.Agarwal
Talks about:transistor (1) worst (1) minim (1) logic (1) group (1) estim (1) delay (1) case (1) bool (1)
Person: Nicholas C. Rumin
DBLP: Rumin:Nicholas_C=
Contributed to:
19891985Wrote 2 papers:
- DAC-1989-GaiottiDR #estimation #worst-case
- Worst-case Delay Estimation of Transistor Groups (SG, MD, NCR), pp. 491–495.
- DAC-1985-DagenaisAR #logic
- The McBOOLE logic minimizer (MD, VKA, NCR), pp. 667–673.