Travelled to:1 × USA
2 × France
Collaborated with:S.Vasudevan J.A.Kumar C.Gu S.Natarajan E.Chiprout
Talks about:circuit (4) analog (3) nonlinear (2) reachabl (2) analysi (2) increment (1) algorithm (1) stimulus (1) generat (1) diagram (1)
Person: Seyed Nematollah Ahmadyan
DBLP: Ahmadyan:Seyed_Nematollah
Contributed to:
20152013
2012Wrote 4 papers:
- DATE-2015-AhmadyanGNCV #analysis #diagrams #performance
- Fast eye diagram analysis for high-speed CMOS circuits (SNA, CG, SN, EC, SV), pp. 1377–1382.
- DATE-2013-AhmadyanKV #algorithm #incremental #runtime #using #verification
- Runtime verification of nonlinear analog circuits using incremental time-augmented RRT algorithm (SNA, JAK, SV), pp. 21–26.
- DATE-2013-AhmadyanV #analysis #reachability #reduction #set
- Reachability analysis of nonlinear analog circuits through iterative reachable set reduction (SNA, SV), pp. 1436–1441.
- DAC-2012-AhmadyanKV #generative
- Goal-oriented stimulus generation for analog circuits (SNA, JAK, SV), pp. 1018–1023.