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Travelled to:
1 × France
3 × USA
Collaborated with:
X.Li E.Chiprout F.Wang S.Youn J.Kim M.Zaheer S.N.Ahmadyan S.Natarajan S.Vasudevan W.Zhang S.Sun C.Fang Q.Huang F.Yang X.Zeng
Talks about:
bayesian (3) circuit (3) signal (3) effici (3) model (3) mix (3) fusion (2) analog (2) speed (2) infer (2)

Person: Chenjie Gu

DBLP DBLP: Gu:Chenjie

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DAC 20132013

Wrote 6 papers:

DAC-2015-ZaheerWGL #markov #named #performance #process
mTunes: efficient post-silicon tuning of mixed-signal/RF integrated circuits based on Markov decision process (MZ, FW, CG, XL), p. 6.
DATE-2015-AhmadyanGNCV #analysis #diagrams #performance
Fast eye diagram analysis for high-speed CMOS circuits (SNA, CG, SN, EC, SV), pp. 1377–1382.
DATE-2015-FangHYZLG #estimation #fault #performance
Efficient bit error rate estimation for high-speed link by Bayesian model fusion (CF, QH, FY, XZ, XL, CG), pp. 1024–1029.
DAC-2014-YounGK #debugging #locality #probability #statistics
Probabilistic Bug Localization via Statistical Inference based on Partially Observed Data (SY, CG, JK), p. 6.
DAC-2013-GuCL #estimation #performance #validation
Efficient moment estimation with extremely small sample size via bayesian inference for analog/mixed-signal validation (CG, EC, XL), p. 7.
DAC-2013-WangZSLG #modelling #performance #reuse #scalability
Bayesian model fusion: large-scale performance modeling of analog and mixed-signal circuits by reusing early-stage data (FW, WZ, SS, XL, CG), p. 6.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.