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Collaborated with:
S.Drossopoulou S.K.Lahiri S.Eisenbach
Talks about:
procedur (1) presenc (1) modular (1) equival (1) memori (1) verif (1) alloc (1)

Person: Tim Wood 0004

DBLP DBLP: 0004:Tim_Wood

Contributed to:

ESOP 20172017

Wrote 1 papers:

ESOP-2017-WoodDLE #composition #equivalence #memory management #verification
Modular Verification of Procedure Equivalence in the Presence of Memory Allocation (TW0, SD, SKL, SE), pp. 937–963.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.