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Travelled to:
1 × USA
Collaborated with:
C.J.Myers
Talks about:
circuit (1) automat (1) verif (1) time (1)

Person: Tomas Rokicki

DBLP DBLP: Rokicki:Tomas

Contributed to:

CAV 19941994

Wrote 1 papers:

CAV-1994-RokickiM #automation #verification
Automatic Verification of Timed Circuits (TR, CJM), pp. 468–480.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.