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Travelled to:
1 × Canada
1 × Denmark
1 × France
3 × USA
Collaborated with:
W.Belluomini T.Rokicki H.Lin P.Li T.Yoneda T.Kitai H.Zheng E.Mercer T.Neupane C.Madsen H.Z.0001 Z.Z.0006
Talks about:
verif (5) circuit (4) time (4) automat (3) analysi (3) system (2) constraint (1) reachabl (1) approxim (1) abstract (1)

Person: Chris J. Myers

DBLP DBLP: Myers:Chris_J=

Contributed to:

DAC 20132013
CAV 20122012
CAV 20022002
CAV 20012001
CAV 19981998
CAV 19941994
CAV (1) 20192019

Wrote 7 papers:

DAC-2013-LinLM #analysis #hybrid #kernel #reachability #verification
Verification of digitally-intensive analog circuits via kernel ridge regression and hybrid reachability analysis (HL, PL, CJM), p. 6.
CAV-2012-Myers #search-based #verification
Formal Verification of Genetic Circuits (CJM), p. 5.
CAV-2002-YonedaKM #analysis #automation #constraints
Automatic Derivation of Timing Constraints by Failure Analysis (TY, TK, CJM), pp. 195–208.
CAV-2001-ZhengMM #abstraction #automation #verification
Automatic Abstraction for Verification of Timed Circuits and Systems (HZ, EM, CJM), pp. 182–193.
CAV-1998-BelluominiM #using #verification
Verification of Timed Systems Using POSETs (WB, CJM), pp. 403–415.
CAV-1994-RokickiM #automation #verification
Automatic Verification of Timed Circuits (TR, CJM), pp. 468–480.
CAV-2019-NeupaneMM00 #analysis #approximate #infinity #model checking #named #probability
STAMINA: STochastic Approximate Model-Checker for INfinite-State Analysis (TN, CJM, CM, HZ0, ZZ0), pp. 540–549.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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