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Travelled to:
1 × USA
Collaborated with:
F.Yuan Q.Xu
Talks about:
synthesi (1) circuit (1) specul (1) effici (1) level (1) time (1) cost (1)

Person: Yuxi Liu

DBLP DBLP: Liu:Yuxi

Contributed to:

DAC 20112011

Wrote 1 papers:

DAC-2011-LiuYX #low cost
Re-synthesis for cost-efficient circuit-level timing speculation (YL, FY, QX), pp. 158–163.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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