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Travelled to:
2 × France
3 × Germany
7 × USA
Collaborated with:
Q.Xu L.Huang R.Ye J.Zhang X.Liu Y.Liu Q.Zhang W.Jone L.Wei Z.Sun Y.Liu H.Zhou Y.Zhang T.Wang Y.Tian
Talks about:
time (7) test (6) specul (5) circuit (4) framework (2) function (2) approxim (2) schedul (2) reliabl (2) network (2)

Person: Feng Yuan

DBLP DBLP: Yuan:Feng

Contributed to:

DAC 20152015
DATE 20152015
DAC 20142014
DAC 20132013
DAC 20122012
DATE 20122012
DAC 20112011
DATE 20102010
DAC 20092009
DATE 20092009
DAC 20082008
DATE 20082008

Wrote 16 papers:

DAC-2015-LiuZWYX #analysis #difference #encryption #fault #named
DERA: yet another differential fault attack on cryptographic devices based on error rate analysis (YL, JZ, LW, FY, QX), p. 6.
DATE-2015-YeYZX #on the
On the premises and prospects of timing speculation (RY, FY, JZ, QX), pp. 605–608.
DATE-2015-ZhangWTYX #approximate #framework #named #network
ApproxANN: an approximate computing framework for artificial neural network (QZ, TW, YT, FY, QX), pp. 701–706.
DAC-2014-ZhangYYX #approximate #framework #named
ApproxIt: An Approximate Computing Framework for Iterative Methods (QZ, FY, RY, QX), p. 6.
DAC-2013-YeYSJX #generative
Post-placement voltage island generation for timing-speculative circuits (RY, FY, ZS, WBJ, QX), p. 6.
DAC-2013-YuanLJX #on the #testing
On testing timing-speculative circuits (FY, YL, WBJ, QX), p. 6.
DAC-2013-YuanX #fault #logic #low cost #named #scalability
InTimeFix: a low-cost and scalable technique for in-situ timing error masking in logic circuits (FY, QX), p. 6.
DAC-2013-ZhangYWSX #hardware #named #trust #verification
VeriTrust: verification for hardware trust (JZ, FY, LW, ZS, QX), p. 8.
DAC-2012-YuanLX #configuration management #debugging #named
X-tracer: a reconfigurable X-tolerant trace compressor for silicon debug (FY, XL, QX), pp. 555–560.
DATE-2012-YeYZX #scheduling
Clock skew scheduling for timing speculation (RY, FY, HZ, QX), pp. 929–934.
DAC-2011-LiuYX #low cost
Re-synthesis for cost-efficient circuit-level timing speculation (YL, FY, QX), pp. 158–163.
DATE-2010-LiuZYX #power management #pseudo #testing
Layout-aware pseudo-functional testing for critical paths considering power supply noise effects (XL, YZ, FY, QX), pp. 1432–1437.
DAC-2009-YuanX #identification #on the #pseudo #testing
On systematic illegal state identification for pseudo-functional testing (FY, QX), pp. 702–707.
DATE-2009-HuangYX #scheduling
Lifetime reliability-aware task allocation and scheduling for MPSoC platforms (LH, FY, QX), pp. 51–56.
DAC-2008-HuangYX #composition #on the #reliability #testing
On reliable modular testing with vulnerable test access mechanisms (LH, FY, QX), pp. 834–839.
Re-Examining the Use of Network-on-Chip as Test Access Mechanism (FY, LH, QX), pp. 808–811.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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