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Travelled to:
1 × Ireland
1 × Italy
Collaborated with:
J.Wang Z.Liu Y.Zhang W.Dong H.Yu J.W.0001 W.D.0006
Talks about:
properti (2) regular (2) symbol (2) guid (2) executor (1) communic (1) process (1) compens (1) failur (1) execut (1)

Person: Zhenbang Chen

DBLP DBLP: Chen:Zhenbang

Contributed to:

ICSE 20152015
FM 20112011
ESEC/FSE 20172017

Wrote 3 papers:

ICSE-v1-2015-ZhangCWD0 #execution #symbolic computation
Regular Property Guided Dynamic Symbolic Execution (YZ, ZC, JW, WD, ZL), pp. 643–653.
FM-2011-ChenLW #communication #process #refinement
Failure-Divergence Refinement of Compensating Communicating Processes (ZC, ZL, JW), pp. 262–277.
ESEC-FSE-2017-YuCZWD #java #named
RGSE: a regular property guided symbolic executor for Java (HY, ZC, YZ, JW0, WD0), pp. 954–958.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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