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Travelled to:
1 × Italy
1 × Singapore
6 × USA
Collaborated with:
P.Li W.Fu M.Charikar K.Li X.Ye G.Yu Z.Feng Y.Zhang Z.Chen J.Wang Z.Liu Z.Wang W.Josephson
Talks about:
simul (3) paralleliz (2) circuit (2) effici (2) model (2) time (2) uncertainti (1) transient (1) precondit (1) framework (1)

Person: Wei Dong

DBLP DBLP: Dong:Wei

Contributed to:

ICSE 20152015
CSCW 20122012
CHI 20102010
DAC 20092009
CIKM 20082008
DAC 20082008
SIGIR 20082008
DAC 20072007

Wrote 9 papers:

ICSE-v1-2015-ZhangCWD0 #execution #symbolic computation
Regular Property Guided Dynamic Symbolic Execution (YZ, ZC, JW, WD, ZL), pp. 643–653.
CSCW-2012-DongF #communication #why
One piece at a time: why video-based communication is better for negotiation and conflict resolution (WD, WTF), pp. 167–176.
CHI-2010-DongF #difference #image
Cultural difference in image tagging (WD, WTF), pp. 981–984.
DAC-2009-DongL #integration #performance #simulation
Parallelizable stable explicit numerical integration for efficient circuit simulation (WD, PL), pp. 382–385.
CIKM-2008-DongWJCL #modelling #performance
Modeling LSH for performance tuning (WD, ZW, WJ, MC, KL), pp. 669–678.
DAC-2008-DongLY #manycore #named #parallel #simulation
WavePipe: parallel transient simulation of analog and digital circuits on multi-core shared-memory machines (WD, PL, XY), pp. 238–243.
SIGIR-2008-DongCL #distance #estimation #similarity #sketching #symmetry
Asymmetric distance estimation with sketches for similarity search in high-dimensional spaces (WD, MC, KL), pp. 123–130.
DAC-2007-DongL #performance #simulation #using
Accelerating Harmonic Balance Simulation Using Efficient Parallelizable Hierarchical Preconditioning (WD, PL), pp. 436–439.
DAC-2007-YuDFL #analysis #framework #nondeterminism #process #statistics
A Framework for Accounting for Process Model Uncertainty in Statistical Static Timing Analysis (GY, WD, ZF, PL), pp. 829–834.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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