9 papers:
DATE-2015-RajendranRadhika- Path selection based acceleration of conditionals in CGRAs (SR, AS, MH), pp. 121–126.
- DATE-2015-YinLLWG #pipes and filters
- Joint affine transformation and loop pipelining for mapping nested loop on CGRAs (SY, DL, LL, SW, YG), pp. 115–120.
DAC-2014-HamzehSV- Branch-Aware Loop Mapping on CGRAs (MH, AS, SBKV), p. 6.
- DAC-2013-HamzehSV #architecture #configuration management #named
- REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs) (MH, AS, SBKV), p. 10.
- DAC-2013-LiuYLW #modelling #optimisation
- Polyhedral model based mapping optimization of loop nests for CGRAs (DL, SY, LL, SW), p. 8.
- DATE-2013-HanCL #compilation
- Compiling control-intensive loops for CGRAs with state-based full predication (KH, KC, JL), pp. 1579–1582.
- DATE-2013-LeeJS #architecture #hybrid #memory management #performance
- Fast shared on-chip memory architecture for efficient hybrid computing with CGRAs (JL, YJ, SS), pp. 1575–1578.
- DAC-2012-HamzehSV #morphism #named #using
- EPIMap: using epimorphism to map applications on CGRAs (MH, AS, SBKV), pp. 1284–1291.
LCTES-2010-KimLSP #memory management #multi- Operation and data mapping for CGRAs with multi-bank memory (YK, JL, AS, YP), pp. 17–26.
