Stem edc$ (all stems)

2 papers:

DATE-2013-MaricAV #architecture #hybrid #performance #reliability #using

Efficient cache architectures for reliable hybrid voltage operation using EDC codes (BM, JA, MV), pp. 917–920.

DATE-2006-RossiSM #analysis

Analysis of the impact of bus implemented EDCs on on-chip SSN (DR, CS, CM), pp. 59–64.