BibSLEIGH — voltag stem

Used together with:

scale (59)
power (49)
dynam (47)
low (40)
time (39)

Stem voltag$ (all stems)

208 papers:

DAC-2015-LiuSZLQ #generative #statistics: A statistical methodology for noise sensor placement and full-chip voltage map generation (XL, SS, PZ, XL, HQ), p. 6.
DAC-2015-TavanaHPSH #named #scalability: ElasticCore: enabling dynamic heterogeneity with joint core and voltage/frequency scaling (MKT, MHH, DP, IS, HH), p. 6.
DAC-2015-TziantzioulisGF #correlation #fault #float #integer #named: b-HiVE: a bit-level history-based error model with value correlation for voltage-scaled integer and floating point units (GT, AMG, SMF, NH, SOM, SP), p. 6.
DAC-2015-YuUK: Leveraging on-chip voltage regulators as a countermeasure against side-channel attacks (WY, OAU, SK), p. 6.
DATE-2015-CilingirogluZUK #representation: Dictionary-based sparse representation for resolution improvement in laser voltage imaging of CMOS integrated circuits (TBC, MZ, AU, WCK, JK, AJ, BBG, MSÜ), pp. 597–600.
DATE-2015-ErolOSPB #metric #using: On-chip measurement of bandgap reference voltage using a small form factor VCO based zoom-in ADC (OEE, SO, CKHS, RAP, LB), pp. 1559–1562.
DATE-2015-GarciaMSN #multi #performance: High performance single supply CMOS inverter level up shifter for multi: supply voltages domains (JCG, JAMN, JS, SN), pp. 1273–1276.
DATE-2015-LiXWNP #fine-grained #multi #power management #reduction #using: Leakage power reduction for deeply-scaled FinFET circuits operating in multiple voltage regimes using fine-grained gate-length biasing technique (JL, QX, YW, SN, MP), pp. 1579–1582.
DATE-2015-VijayakumarK #design #modelling #novel: A novel modeling attack resistant PUF design based on non-linear voltage transfer characteristics (AV, SK), pp. 653–658.
DATE-2015-ZwergerG #detection #symmetry: Detection of asymmetric aging-critical voltage conditions in analog power-down mode (MZ, HEG), pp. 1269–1272.
KDD-2015-MitraKBASMSL #correlation: Voltage Correlations in Smart Meter Data (RM, RK, SB, VA, BS, RM, HS, GL), pp. 1999–2008.
HPCA-2015-HsuZLMWMTD #named #query: Adrenaline: Pinpointing and reining in tail queries with quick voltage boosting (CHH, YZ, MAL, DM, TFW, JM, LT, RGD), pp. 271–282.
HPCA-2015-LengZR #architecture #gpu: GPU voltage noise: Characterization and hierarchical smoothing of spatial and temporal voltage noise interference in GPU architectures (JL, YZ, VJR), pp. 161–173.
CASE-2014-HsuehTLKY #estimation: Voltage-current-based state and disturbance estimation for power-assisted control applied to an electric wheelchair (PWH, MCT, CYL, PJK, WSY), pp. 1220–1225.
DAC-2014-ChenWLWSC #design #monitoring #scalability: Critical Path Monitor Enabled Dynamic Voltage Scaling for Graceful Degradation in Sub-Threshold Designs (YGC, TW, KYL, WYW, YS, SCC), p. 6.
DAC-2014-Kose #challenge: Thermal Implications of On-Chip Voltage Regulation: Upcoming Challenges and Possible Solutions (SK), p. 6.
DAC-2014-MotamanG #array #robust #self #testing: Simultaneous Sizing, Reference Voltage and Clamp Voltage Biasing for Robustness, Self-Calibration and Testability of STTRAM Arrays (SM, SG), p. 2.
DAC-2014-WangMZSS: Walking Pads: Managing C4 Placement for Transient Voltage Noise Minimization (KW, BHM, RZ, MRS, KS), p. 6.
DAC-2014-WangX #on the #performance #simulation: On the Simulation of NBTI-Induced Performance Degradation Considering Arbitrary Temperature and Voltage Variations (TW, QX), p. 6.
DATE-2014-BortolottiBWRB #architecture #hybrid #manycore #memory management #power management #scalability: Hybrid memory architecture for voltage scaling in ultra-low power multi-core biomedical processors (DB, AB, CW, DR, LB), pp. 1–6.
DATE-2014-LeeWP #configuration management #framework #manycore #named: VRCon: Dynamic reconfiguration of voltage regulators in a multicore platform (WL, YW, MP), pp. 1–6.
DATE-2014-MacrelliWRHPTR #design #energy: Design and fabrication of a 315 μΗ bondwire micro-transformer for ultra-low voltage energy harvesting (EM, NW, SR, MH, RPP, MT, AR), pp. 1–4.
DATE-2014-PuEMG #logic #power management #scalability #synthesis: Logic synthesis of low-power ICs with ultra-wide voltage and frequency scaling (YP, JDE, MM, JPdG), pp. 1–2.
DATE-2014-SilvanoPXS #architecture #manycore: Voltage island management in near threshold manycore architectures to mitigate dark silicon (CS, GP, SX, ISS), pp. 1–6.
DATE-2014-WangXWCWW #manycore #power management: Characterizing power delivery systems with on/off-chip voltage regulators for many-core processors (XW, JX, ZW, KJC, XW, ZW), pp. 1–4.
DATE-2014-ZschieschangRKTZLBRBXMK #flexibility: Low-voltage organic transistors for flexible electronics (UZ, RR, UK, KT, TZ, FL, JB, HR, JNB, WX, BM, HK), pp. 1–6.
CGO-2014-JimboreanKSBK #approach #compilation #hardware #scalability: Fix the code. Don’t tweak the hardware: A new compiler approach to Voltage-Frequency scaling (AJ, KK, VS, DBS, SK), p. 262.
HPCA-2014-AnsariMXT #energy #named #network: Tangle: Route-oriented dynamic voltage minimization for variation-afflicted, energy-efficient on-chip networks (AA, AKM, JX, JT), pp. 440–451.
HPCA-2014-KarpuzcuAK #named #towards: Accordion: Toward soft Near-Threshold Voltage Computing (URK, IA, NSK), pp. 72–83.
DAC-2013-CalimeraMP #constraints #energy #fault #scheduling: Energy-optimal SRAM supply voltage scheduling under lifetime and error constraints (AC, EM, MP), p. 6.
DAC-2013-ChakrabortyLAP #physics: A transmission gate physical unclonable function and on-chip voltage-to-digital conversion technique (RC, CL, DA, JP), p. 10.
DAC-2013-ChenXKGHKOA #design #manycore #scalability: Dynamic voltage and frequency scaling for shared resources in multicore processor designs (XC, ZX, HK, PVG, JH, MK, ÜYO, RZA), p. 7.
DAC-2013-MaricAV #adaptation #energy #hybrid #named #predict #reliability: APPLE: adaptive performance-predictable low-energy caches for reliable hybrid voltage operation (BM, JA, MV), p. 8.
DAC-2013-YeYSJX #generative: Post-placement voltage island generation for timing-speculative circuits (RY, FY, ZS, WBJ, QX), p. 6.
DATE-2013-BeigneVGTBTBMBMFNAPGCRCEW #design: Ultra-wide voltage range designs in fully-depleted silicon-on-insulator FETs (EB, AV, BG, OT, TB, YT, SB, GM, OB, YM, PF, JPN, FA, BPP, AG, SC, PR, JLC, SE, RW), pp. 613–618.
DATE-2013-CaiHMM #analysis #memory management #modelling: Threshold voltage distribution in MLC NAND flash memory: characterization, analysis, and modeling (YC, EFH, OM, KM), pp. 1285–1290.
DATE-2013-ChanCK #adaptation #scalability: Impact of adaptive voltage scaling on aging-aware signoff (TBC, WTJC, ABK), pp. 1683–1688.
DATE-2013-De #design: Near-threshold voltage design in nanoscale CMOS (VD), p. 612.
DATE-2013-DeutschC #multi #using: Non-invasive pre-bond TSV test using ring oscillators and multiple voltage levels (SD, KC), pp. 1065–1070.
DATE-2013-HeLLHY #streaming #synthesis: Utilizing voltage-frequency islands in C-to-RTL synthesis for streaming applications (XH, SL, YL, XSH, HY), pp. 992–995.
DATE-2013-HuYH0 #concurrent #low cost #multi #named #thread: Orchestrator: a low-cost solution to reduce voltage emergencies for multi-threaded applications (XH, GY, YH, XL), pp. 208–213.
DATE-2013-MaricAV #architecture #hybrid #performance #reliability #using: Efficient cache architectures for reliable hybrid voltage operation using EDC codes (BM, JA, MV), pp. 917–920.
DATE-2013-RethyDSDG #interface #network #power management: A low-power and low-voltage BBPLL-based sensor interface in 130nm CMOS for wireless sensor networks (JVR, HD, VDS, WD, GGEG), pp. 1431–1435.
SAC-2013-HuangMGM #multi #realtime #scalability: Throughput-constrained voltage and frequency scaling for real-time heterogeneous multiprocessors (PH, OM, KG, AMM), pp. 1517–1524.
HPCA-2013-MahmoodKH #adaptation #architecture #named #scalability: Macho: A failure model-oriented adaptive cache architecture to enable near-threshold voltage scaling (TM, SK, SH), pp. 532–541.
DAC-2012-ChenZCZX #mobile #scalability #streaming #video: Quality-retaining OLED dynamic voltage scaling for video streaming applications on mobile devices (XC, JZ, YC, MZ, CJX), pp. 1000–1005.
DAC-2012-GhasemiSSK #effectiveness #power management: Cost-effective power delivery to support per-core voltage domains for power-constrained processors (HRG, AAS, MJS, NSK), pp. 56–61.
DAC-2012-KaulAHAKB #challenge #design: Near-threshold voltage (NTV) design: opportunities and challenges (HK, MA, SH, AA, RK, SB), pp. 1153–1158.
DAC-2012-LionelPSE #monitoring #statistics #testing: Embedding statistical tests for on-chip dynamic voltage and temperature monitoring (LV, PM, SL, EB), pp. 994–999.
DAC-2012-MorrisBZP #logic #named #using: mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices (DM, DB, JG(Z, LTP), pp. 486–491.
DAC-2012-Seok #design: Decoupling capacitor design strategy for minimizing supply noise of ultra low voltage circuits (MS), pp. 968–973.
DATE-2012-DrumlSWGH #estimation #manycore #smarttech: Estimation based power and supply voltage management for future RF-powered multi-core smart cards (ND, CS, RW, AG, JH), pp. 358–363.
DATE-2012-KnothJS #analysis #modelling: Current source modeling for power and timing analysis at different supply voltages (CK, HJ, US), pp. 923–928.
DATE-2012-RahimiBG #analysis: Analysis of instruction-level vulnerability to dynamic voltage and temperature variations (AR, LB, RKG), pp. 1102–1105.
DATE-2012-SinkarWK #manycore #optimisation #performance: Workload-aware voltage regulator optimization for power efficient multi-core processors (AAS, HW, NSK), pp. 1134–1137.
DATE-2012-ZhangPM #3d #analysis #grid #power management: Voltage propagation method for 3-D power grid analysis (CZ, VFP, GDM), pp. 844–847.
HPCA-2012-MillerPTST #named #process: Booster: Reactive core acceleration for mitigating the effects of process variation and application imbalance in low-voltage chips (TNM, XP, RT, NS, RT), pp. 27–38.
HPCA-2012-YanLHLGL #architecture #hybrid #manycore #named #performance: AgileRegulator: A hybrid voltage regulator scheme redeeming dark silicon for power efficiency in a multicore architecture (GY, YL, YH, XL, MG, XL), pp. 287–298.
DAC-2011-FuketaIYTNSS #logic: A closed-form expression for estimating minimum operating voltage (VDDmin) of CMOS logic gates (HF, SI, TY, MT, MN, HS, TS), pp. 984–989.
DAC-2011-KoseF #algorithm #analysis #information retrieval #locality #performance: Fast algorithms for IR voltage drop analysis exploiting locality (SK, EGF), pp. 996–1001.
DAC-2011-SeokJCBS #design #energy #performance #pipes and filters: Pipeline strategy for improving optimal energy efficiency in ultra-low voltage design (MS, DJ, CC, DB, DS), pp. 990–995.
DAC-2011-ShinKCP #scalability: Dynamic voltage scaling of OLED displays (DS, YK, NC, MP), pp. 53–58.
DAC-2011-WeiP #security #using: Integrated circuit security techniques using variable supply voltage (SW, MP), pp. 248–253.
DATE-2011-AlordaTBS #embedded #optimisation #using: Stability optimization of embedded 8T SRAMs using Word-Line Voltage modulation (BA, GT, SAB, JS), pp. 986–991.
DATE-2011-KrauseP #adaptation: Adaptive voltage over-scaling for resilient applications (PKK, IP), pp. 944–949.
DATE-2011-MohapatraCRR #approximate #design: Design of voltage-scalable meta-functions for approximate computing (DM, VKC, AR, KR), pp. 950–955.
DATE-2011-NalamCAC: Dynamic write limited minimum operating voltage for nanoscale SRAMs (SN, VC, RCA, BHC), pp. 467–472.
DATE-2011-PanHHL #effectiveness: A cost-effective substantial-impact-filter based method to tolerate voltage emergencies (SP, YH, XH, XL), pp. 311–315.
DATE-2011-WuDL #multi: Power-driven global routing for multi-supply voltage domains (THW, AD, JTL), pp. 443–448.
DATE-2011-ZhaoDX #3d #design #energy #fine-grained #scalability: An energy-efficient 3D CMP design with fine-grained voltage scaling (JZ, XD, YX), pp. 539–542.
HPCA-2011-GhasemiDK #architecture #using: Low-voltage on-chip cache architecture using heterogeneous cell sizes for high-performance processors (HRG, SCD, NSK), pp. 38–49.
DAC-2010-WangM #approximate #named #realtime #scalability #using: PreDVS: preemptive dynamic voltage scaling for real-time systems using approximation scheme (WW, PM), pp. 705–710.
DAC-2010-ZengYFL #analysis #network #optimisation #power management #trade-off: Tradeoff analysis and optimization of power delivery networks with on-chip voltage regulation (ZZ, XY, ZF, PL), pp. 831–836.
DATE-2010-BaoAEP #energy #optimisation #scalability: Temperature-aware idle time distribution for energy optimization with dynamic voltage scaling (MB, AA, PE, ZP), pp. 21–26.
DATE-2010-ChandraPA #on the: On the efficacy of write-assist techniques in low voltage nanoscale SRAMs (VC, CP, RCA), pp. 345–350.
DATE-2010-FanucciPDSTCLT #programmable: An high voltage CMOS voltage regulator for automotive alternators with programmable functionalities and full reverse polarity capability (LF, GP, PD, RS, FT, PC, LL, PT), pp. 526–531.
DATE-2010-GhoshS #performance #perspective: Power efficient voltage islanding for Systems-on-chip from a floorplanning perspective (PG, AS), pp. 654–657.
DATE-2010-JungP #network #nondeterminism #optimisation #power management: Optimizing the power delivery network in dynamically voltage scaled systems with uncertain power mode transition times (HJ, MP), pp. 351–356.
DATE-2010-LazzariFMC #multi: A new quaternary FPGA based on a voltage-mode multi-valued circuit (CL, PFF, JM, LC), pp. 1797–1802.
DATE-2010-LuPRR #energy #performance #transducer: Efficient power conversion for ultra low voltage micro scale energy transducers (CL, SPP, VR, KR), pp. 1602–1607.
DATE-2010-PasettiFS #power management: A High-Voltage Low-Power DC-DC buck regulator for automotive applications (GP, LF, RS), pp. 937–940.
DATE-2010-RitheGWDGBC #analysis #logic #statistics: Non-linear Operating Point Statistical Analysis for Local Variations in logic timing at low voltage (RR, JG, AW, SD, GG, DB, AC), pp. 965–968.
SAC-2010-GhoshS #constraints #design #energy #performance: Efficient mapping and voltage islanding technique for energy minimization in NoC under design constraints (PG, AS), pp. 535–541.
SAC-2010-Niu #energy #realtime #scalability: Energy-aware dual-mode voltage scaling for weakly hard real-time systems (LN), pp. 321–325.
HPCA-2010-KahngKKS #design #reliability #trade-off: Designing a processor from the ground up to allow voltage/reliability tradeoffs (ABK, SK, RK, JS), pp. 1–11.
DAC-2009-BaoAEP #dependence #energy #online #optimisation #scalability: On-line thermal aware dynamic voltage scaling for energy optimization with frequency/temperature dependency consideration (MB, AA, PE, ZP), pp. 490–495.
DAC-2009-ChangMR #architecture #hybrid #process #video: A voltage-scalable & process variation resilient hybrid SRAM architecture for MPEG-4 video processors (IJC, DM, KR), pp. 670–675.
DAC-2009-GargMMO #design #multi #perspective: Technology-driven limits on DVFS controllability of multiple voltage-frequency island designs: a system-level perspective (SG, DM, RM, ÜYO), pp. 818–821.
DAC-2009-LiuWQ #adaptation #algorithm #energy #realtime #scheduling: An adaptive scheduling and voltage/frequency selection algorithm for real-time energy harvesting systems (SL, QW, QQ), pp. 782–787.
DAC-2009-PanKOMC #process: Selective wordline voltage boosting for caches to manage yield under process variations (YP, JK, SO, GM, SWC), pp. 57–62.
DAC-2009-SeiculescuMBM #synthesis: NoC topology synthesis for supporting shutdown of voltage islands in SoCs (CS, SM, LB, GDM), pp. 822–825.
DAC-2009-ShinPS #synthesis #using: Register allocation for high-level synthesis using dual supply voltages (IS, SP, YS), pp. 937–942.
DATE-2009-ChandraA #reliability #scalability: Impact of voltage scaling on nanoscale SRAM reliability (VC, RCA), pp. 387–392.
DATE-2009-GuptaRHWB #approach: An event-guided approach to reducing voltage noise in processors (MSG, VJR, GHH, GYW, DMB), pp. 160–165.
DATE-2009-KhursheedAH #design #fault #multi #reduction: Test cost reduction for multiple-voltage designs with bridge defects through Gate-Sizing (SSK, BMAH, PH), pp. 1349–1354.
DATE-2009-PaciBB #adaptation #bias #communication #effectiveness #variability: Effectiveness of adaptive supply voltage and body bias as post-silicon variability compensation techniques for full-swing and low-swing on-chip communication channels (GP, DB, LB), pp. 1404–1409.
DATE-2009-SasanHEK #process #scalability: Process Variation Aware SRAM/Cache for aggressive voltage-frequency scaling (AS, HH, AME, FJK), pp. 911–916.
HPCA-2009-HerbertM #scalability: Variation-aware dynamic voltage/frequency scaling (SH, DM), pp. 301–312.
HPCA-2009-ReddiGHWSB #predict #using: Voltage emergency prediction: Using signatures to reduce operating margins (VJR, MSG, GHH, GYW, MDS, DMB), pp. 18–29.
DAC-2008-CaoFHS #algorithm #multi #scalability: Optimality and improvement of dynamic voltage scaling algorithms for multimedia applications (ZC, BF, LH, MvdS), pp. 179–184.
DAC-2008-FeldmannASSBG #analysis #modelling #multi: Driver waveform computation for timing analysis with multiple voltage threshold driver models (PF, SA, DS, GS, RB, HG), pp. 425–428.
DAC-2008-GinsburgC #energy #parallel: The mixed signal optimum energy point: voltage and parallelism (BPG, APC), pp. 244–249.
DAC-2008-KulkarniKPR #array #process: Process variation tolerant SRAM array for ultra low voltage applications (JPK, KK, SPP, KR), pp. 108–113.
DAC-2008-KurimotoSAYOTS #detection #fault #optimisation #scalability: Phase-adjustable error detection flip-flops with 2-stage hold driven optimization and slack based grouping scheme for dynamic voltage scaling (MK, HS, RA, TY, HO, HT, HS), pp. 884–889.
DAC-2008-SenguptaS #design: Application-driven floorplan-aware voltage island design (DS, RAS), pp. 155–160.
DATE-2008-BaoAEP #energy #optimisation: Temperature-Aware Voltage Selection for Energy Optimization (MB, AA, PE, ZP), pp. 1083–1086.
DATE-2008-GargMK: A Single-supply True Voltage Level Shifter (RG, GM, SPK), pp. 979–984.
DATE-2008-HongYBCEK #bias #runtime #scalability: Dynamic Voltage Scaling of Supply and Body Bias Exploiting Software Runtime Distribution (SH, SY, BB, KMC, SKE, TK), pp. 242–247.
DATE-2008-LiuQW #energy #realtime: Energy Aware Dynamic Voltage and Frequency Selection for Real-Time Systems with Energy Harvesting (SL, QQ, QW), pp. 236–241.
DATE-2008-MalaniMQW #adaptation #multi #nondeterminism #realtime #scalability #scheduling: Adaptive Scheduling and Voltage Scaling for Multiprocessor Real-time Applications with Non-deterministic Workload (PM, PM, QQ, QW), pp. 652–657.
DATE-2008-StefanoBBM #design #multi #pipes and filters #process: Process Variation Tolerant Pipeline Design Through a Placement-Aware Multiple Voltage Island Design Style (BS, DB, LB, EM), pp. 967–972.
DATE-2008-ZhangZYZSPZCMSIC #multi #network: Finding the Worst Voltage Violation in Multi-Domain Clock Gated Power Network (WZ, YZ, WY, LZ, RS, HP, ZZ, LCE, RM, TS, NI, CKC), pp. 537–540.
DAC-2007-AhmedTJ #design #fault #generative: Transition Delay Fault Test Pattern Generation Considering Supply Voltage Noise in a SOC Design (NA, MT, VJ), pp. 533–538.
DAC-2007-AmelifardP #network #power management: Optimal Selection of Voltage Regulator Modules in a Power Delivery Network (BA, MP), pp. 168–173.
DAC-2007-GuSK #modelling #random #statistics: Width-dependent Statistical Leakage Modeling for Random Dopant Induced Threshold Voltage Shift (JG, SSS, CHK), pp. 87–92.
DAC-2007-HariziHOB #analysis #modelling #performance: Efficient Modeling Techniques for Dynamic Voltage Drop Analysis (HH, RH, MO, EB), pp. 706–711.
DAC-2007-LeungT #energy #synthesis: Energy-Aware Synthesis of Networks-on-Chip Implemented with Voltage Islands (LFL, CYT), pp. 128–131.
DAC-2007-LiuLC #algorithm #approximate #multi #optimisation #using: A Provably Good Approximation Algorithm for Power Optimization Using Multiple Supply Voltages (HYL, WPL, YWC), pp. 887–890.
DAC-2007-OgrasMCM #clustering: Voltage-Frequency Island Partitioning for GALS-based Networks-on-Chip (ÜYO, RM, PC, DM), pp. 110–115.
DAC-2007-WuW #detection #incremental: Improving Voltage Assignment by Outlier Detection and Incremental Placement (HW, MDFW), pp. 459–464.
DATE-2007-GargM #analysis #design #interactive #multi #process #throughput: Interactive presentation: System-level process variation driven throughput analysis for single and multiple voltage-frequency island designs (SG, DM), pp. 403–408.
DATE-2007-GhoshBR #adaptation #scheduling #synthesis #using: Low-overhead circuit synthesis for temperature adaptation using dynamic voltage scheduling (SG, SB, KR), pp. 1532–1537.
DATE-2007-GuptaOJWB #comprehension #distributed #multi #network #using: Understanding voltage variations in chip multiprocessors using a distributed power-delivery network (MSG, JLO, RJ, GYW, DMB), pp. 624–629.
DATE-2007-HwangCR #interactive #process #scalability: Interactive presentation: Process tolerant beta-ratio modulation for ultra-dynamic voltage scaling (MEH, TC, KR), pp. 1550–1555.
DATE-2007-LasbouyguesWAM #analysis: Temperature and voltage aware timing analysis: application to voltage drops (BL, RW, NA, PM), pp. 1012–1017.
DATE-2007-QuSN #configuration management #energy #interactive #runtime #scalability #using: Interactive presentation: Using dynamic voltage scaling to reduce the configuration energy of run time reconfigurable devices (YQ, JPS, JN), pp. 147–152.
SAC-2007-KimmSS #algorithm #evaluation #linux #mobile #scalability: Evaluation of interval-based dynamic voltage scaling algorithms on mobile Linux system (HK, SYS, COS), pp. 1141–1145.
LCTES-2007-AbouGhazalehFRXLCMM #cpu #machine learning #scalability #using: Integrated CPU and l2 cache voltage scaling using machine learning (NA, APF, CR, RX, FL, BRC, DM, RGM), pp. 41–50.
LCTES-2007-ZhuM #feedback #named #reduction #scalability #scheduling: DVSleak: combining leakage reduction and voltage scaling in feedback EDF scheduling (YZ, FM), pp. 31–40.
DAC-2006-HuangG #embedded #scalability: Leakage-aware intraprogram voltage scaling for embedded processors (PKH, SG), pp. 364–369.
DAC-2006-PandeyG #communication #constraints #scalability #statistics #synthesis: Statistical on-chip communication bus synthesis and voltage scaling under timing yield constraint (SP, MG), pp. 663–668.
DAC-2006-WuWL: Timing-constrained and voltage-island-aware voltage assignment (HW, MDFW, IML), pp. 429–432.
DATE-2006-BabighianBMM: Enabling fine-grain leakage management by voltage anchor insertion (PB, LB, AM, EM), pp. 868–873.
DATE-2006-BudnikR #distributed #network #novel #power management #using: Minimizing ohmic loss and supply voltage variation using a novel distributed power supply network (MMB, KR), pp. 1116–1121.
DATE-2006-GarciaMN: Bootstrapped full--swing CMOS driver for low supply voltage operation (JCG, JAMN, SN), pp. 410–411.
DATE-2006-HuangG06a #adaptation #compilation #embedded #power management #scalability: Power-aware compilation for embedded processors with dynamic voltage scaling and adaptive body biasing capabilities (PKH, SG), pp. 943–944.
DATE-2006-LuZSLS #scheduling #set: Procrastinating voltage scheduling with discrete frequency sets (ZL, YZ, MRS, JL, KS), pp. 456–461.
DATE-DF-2006-BarontiDKMRSSSV: FlexRay transceiver in a 0.35 µm CMOS high-voltage technology (FB, PD, MK, RM, RR, RS, MS, RS, VV), pp. 201–205.
PLDI-2006-ChenLKI #energy #scalability: Reducing NoC energy consumption through compiler-directed channel voltage scaling (GC, FL, MTK, MJI), pp. 193–203.
ICPR-v4-2006-ZhangY06a #recognition: Insulators Recognition for 220kv/330kv High-voltage Live-line Cleaning Robot (JZ, RY), pp. 630–633.
LCTES-2006-ChenK #scalability #scheduling: Procrastination for leakage-aware rate-monotonic scheduling on a dynamic voltage scaling processor (JJC, TWK), pp. 153–162.
DAC-2005-AziziKDN #design #power management #scalability: Variations-aware low-power design with voltage scaling (NA, MMK, VD, FNN), pp. 529–534.
DAC-2005-CortesEP #energy #realtime: Quasi-static assignment of voltages and optional cycles for maximizing rewards in real-time systems with energy c-onstraints (LAC, PE, ZP), pp. 889–894.
DAC-2005-GaoH #multi #reduction: Total power reduction in CMOS circuits via gate sizing and multiple threshold voltages (FG, JPH), pp. 31–36.
DAC-2005-YanZJ #interactive #latency #scalability: User-perceived latency driven voltage scaling for interactive applications (LY, LZ, NKJ), pp. 624–627.
DAC-2005-ZhangLLSS #realtime #scheduling: Optimal procrastinating voltage scheduling for hard real-time systems (YZ, ZL, JL, KS, MRS), pp. 905–908.
DATE-2005-AndreiSEPH #constraints #energy #scalability: Quasi-Static Voltage Scaling for Energy Minimization with Time Constraints (AA, MTS, PE, ZP, BMAH), pp. 514–519.
DATE-2005-YangWVSX #approach #design: Power Attack Resistant Cryptosystem Design: A Dynamic Voltage and Frequency Switching Approach (SY, WW, NV, DNS, YX), pp. 64–69.
HPCA-2005-WuJMC #adaptation #multi: Voltage and Frequency Control With Adaptive Reaction Time in Multiple-Clock-Domain Processors (QW, PJ, MM, DWC), pp. 178–189.
LCTES-2005-ZhuM #feedback #scalability #scheduling: Feedback EDF scheduling exploiting hardware-assisted asynchronous dynamic voltage scaling (YZ, FM), pp. 203–212.
DAC-2004-BasuLWMB #optimisation #power management: Simultaneous optimization of supply and threshold voltages for low-power and high-performance circuits in the leakage dominant era (AB, SCL, VW, AM, KB), pp. 884–887.
DAC-2004-ChoiSP #scalability: Off-chip latency-driven dynamic voltage and frequency scaling for an MPEG decoding (KC, RS, MP), pp. 544–549.
DAC-2004-DeleganesBGKSW #integer #logic: Low voltage swing logic circuits for a Pentium 4 processor integer core (DJD, MB, GG, KK, APS, SW), pp. 678–680.
DAC-2004-JejurikarPG #embedded #realtime #scalability: Leakage aware dynamic voltage scaling for real-time embedded systems (RJ, CP, RKG), pp. 275–280.
DAC-2004-SeoKC #realtime #scheduling: Profile-based optimal intra-task voltage scheduling for hard real-time applications (JS, TK, KSC), pp. 87–92.
DAC-2004-ZhaiBSF #scalability: Theoretical and practical limits of dynamic voltage scaling (BZ, DB, DS, KF), pp. 868–873.
DATE-DF-2004-FlautnerFRP #energy #named #performance #scalability: IEM926: An Energy Efficient SoC with Dynamic Voltage Scaling (KF, DF, DR, DIP), pp. 324–329.
DATE-v1-2004-AndreiSEPA #energy #reduction: Overhead-Conscious Voltage Selection for Dynamic and Leakage Energy Reduction of Time-Constrained Systems (AA, MTS, PE, ZP, BMAH), pp. 518–525.
DATE-v1-2004-ChoiSP #energy #fine-grained #performance #precise #scalability #trade-off: Fine-Grained Dynamic Voltage and Frequency Scaling for Precise Energy and Performance Trade-Off Based on the Ratio of Off-Chip Access to On-Chip Computation Times (KC, RS, MP), pp. 4–9.
DATE-v2-2004-NaculG #configuration management #power management: Dynamic Voltage and Cache Reconfiguration for Low Power (ACN, TG), pp. 1376–1379.
DATE-v2-2004-ZhangC #analysis #embedded #fault tolerance #realtime #scalability: Task Feasibility Analysis and Dynamic Voltage Scaling in Fault-Tolerant Real-Time Embedded Systems (YZ, KC), pp. 1170–1175.
ASPLOS-2004-WuJMC #multi #online: Formal online methods for voltage/frequency control in multiple clock domain microprocessors (QW, PJ, MM, DWC), pp. 248–259.
LCTES-2004-ImH #multi #realtime #scalability #scheduling #using: Dynamic voltage scaling for real-time multi-task scheduling using buffers (CI, SH), pp. 88–94.
DAC-2003-FerzliN #estimation #grid #power management #process #statistics: Statistical estimation of leakage-induced power grid voltage drop considering within-die process variations (IAF, FNN), pp. 856–859.
DAC-2003-KouroussisN #grid #independence #power management #verification: A static pattern-independent technique for power grid voltage integrity verification (DK, FNN), pp. 99–104.
DAC-2003-KwonK: Optimal voltage allocation techniques for dynamically variable voltage processors (WCK, TK), pp. 125–130.
DAC-2003-LeeB #reduction: Static leakage reduction through simultaneous threshold voltage and state assignment (DL, DB), pp. 191–194.
DATE-2003-LuoPJ #communication #distributed #embedded #realtime #scalability: Simultaneous Dynamic Voltage Scaling of Processors and Communication Links in Real-Time Distributed Embedded Systems (JL, LSP, NKJ), pp. 11150–11151.
PLDI-2003-XieMM #scalability: Compile-time dynamic voltage scaling settings: opportunities and limits (FX, MM, SM), pp. 49–62.
HPCA-2003-JosephBM #performance: Control Techniques to Eliminate Voltage Emergencies in High Performance Processors (RJ, DMB, MM), pp. 79–90.
HPCA-2003-ShangPJ #network #optimisation #scalability: Dynamic Voltage Scaling with Links for Power Optimization of Interconnection Networks (LS, LSP, NKJ), pp. 91–102.
DAC-2002-JungKK #logic: Low-swing clock domino logic incorporating dual supply and dual threshold voltages (SOJ, KWK, SMK), pp. 467–472.
DAC-2002-KangSC #power management #synthesis: An optimal voltage synthesis technique for a power-efficient satellite application (DIK, JS, SPC), pp. 492–497.
DAC-2002-RakhmatovVC #scalability: Battery-conscious task sequencing for portable devices including voltage/clock scaling (DNR, SBKV, CC), pp. 189–194.
DAC-2002-ZhangHC #energy #scheduling: Task scheduling and voltage selection for energy minimization (YZ, XH, DZC), pp. 183–188.
DATE-2002-AzevedoICGDVN #scheduling #using: Profile-Based Dynamic Voltage Scheduling Using Program Checkpoints (AA, II, RC, RG, NDD, AVV, AN), pp. 168–175.
DATE-2002-JungKK #logic #performance #synthesis: Dual Threshold Voltage Domino Logic Synthesis for High Performance with Noise and Power Constrain (SOJ, KWK, SMK), pp. 260–265.
DATE-2002-KimKM #algorithm #analysis #realtime #scalability #using: A Dynamic Voltage Scaling Algorithm for Dynamic-Priority Hard Real-Time Systems Using Slack Time Analysis (WK, JK, SLM), pp. 788–794.
DATE-2002-QuanH #energy #scheduling: Minimum Energy Fixed-Priority Scheduling for Variable Voltage Processor (GQ, XH), pp. 782–787.
DATE-2002-RahajandraibeDACMC #parametricity: Test Structure for IC(VBE) Parameter Determination of Low Voltage Applications (WR, CD, DA, BC, BM, VC), pp. 316–321.
HPCA-2002-GrochowskiAT #architecture #power management #simulation: Microarchitectural Simulation and Control of di/dt-induced Power Supply Voltage Variation (EG, DA, VT), pp. 7–16.
HPCA-2002-SemeraroMBADS #design #energy #multi #scalability #using: Energy-Efficient Processor Design Using Multiple Clock Domains with Dynamic Voltage and Frequency Scaling (GS, GM, RB, DHA, SD, MLS), pp. 29–42.
LCTES-SCOPES-2002-SaputraKVIHHK #compilation #energy #scalability: Energy-conscious compilation based on voltage scaling (HS, MTK, NV, MJI, JSH, CHH, UK), pp. 2–11.
DAC-2001-KimJSLK #optimisation #using: Coupling Delay Optimization by Temporal Decorrelation using Dual Threshold Voltage Technique (KWK, SOJ, PS, CLL, SMK), pp. 732–737.
DAC-2001-QuanH #energy #performance #realtime #scheduling: Energy Efficient Fixed-Priority Scheduling for Real-Time Systems on Variable Voltage Processors (GQ, XH), pp. 828–833.
DAC-2001-ShinKL #analysis #energy #scheduling #using: Low-Energy Intra-Task Voltage Scheduling Using Static Timing Analysis (DS, JK, SL), pp. 438–443.
DAC-2001-SimunicBAGM #power management #scalability: Dynamic Voltage Scaling and Power Management for Portable Systems (TS, LB, AA, PWG, GDM), pp. 524–529.
DATE-2001-DessoukyKLG #case study #design #reuse: Analog design for reuse — case study: very low-voltage sigma-delta modulator (MD, AK, MML, AG), pp. 353–360.
DATE-2001-GerfersM #design #power management: A design strategy for low-voltage low-power continuous-time sigma-delta A/D converters (FG, YM), pp. 361–369.
DATE-2001-YildizSV #bias #float #integer #linear #programming: Minimizing the number of floating bias voltage sources with integer linear programming (EY, AvS, CJMV), p. 816.
LCTES-OM-2001-KimH #embedded #hybrid #power management #realtime #runtime #scalability: Hybrid Run-time Power Management Technique for Real-time Embedded System with Voltage Scalable Processor (MK, SH), pp. 11–19.
SOSP-2001-PillaiS #embedded #operating system #power management #realtime #scalability: Real-Time Dynamic Voltage Scaling for Low-Power Embedded Operating Systems (PP, KGS), pp. 89–102.
DAC-2000-LeeS #power management #realtime #runtime: Run-time voltage hopping for low-power real-time systems (SL, TS), pp. 806–809.
DATE-2000-MetraFR #online #testing: On-Line Testing and Diagnosis of Bus Lines with respect to Intermediate Voltage Values (CM, MF, BR), p. 763.
DAC-1999-NarayanR #multi #simulation: Multi-Time Simulation of Voltage-Controlled Oscillators (ON, JSR), pp. 629–634.
DAC-1999-SirichotiyakulEOZDPB #power management: Stand-by Power Minimization Through Simultaneous Threshold Voltage Selection and Circuit Sizing (SS, TE, CO, JZ, AD, RP, DB), pp. 436–441.
DAC-1999-SundararajanP #power management #synthesis #using: Synthesis of Low Power CMOS VLSI Circuits Using Dual Supply Voltages (VS, KKP), pp. 72–75.
DAC-1999-YehCCJ #design: Gate-Level Design Exploiting Dual Supply Voltages for Power-Driven Applications (CWY, MCC, SCC, WBJ), pp. 68–71.
DAC-1999-YehKSW #design #layout: Layout Techniques Supporting the Use of Dual Supply Voltages for Cell-based Designs (CWY, YSK, SJS, JSW), pp. 62–67.
DATE-1999-StopjakovaMS #monitoring #testing: On-Chip Transient Current Monitor for Testing of Low Voltage CMOS IC (VS, HARM, MS), pp. 538–542.
DAC-1998-HongKQPS #optimisation: Power Optimization of Variable Voltage Core-Based Systems (IH, DK, GQ, MP, MBS), pp. 176–181.
DAC-1998-UsamiIIKTHATK #design #power management #scalability: Design Methodology of Ultra Low-Power MPEG4 Codec Core Exploiting Voltage Scaling Techniques (KU, MI, TI, MK, MT, MH, HA, TT, TK), pp. 483–488.
DAC-1998-WeiCJRD #design #optimisation #performance: Design and Optimization of Low Voltage High Performance Dual Threshold CMOS Circuits (LW, ZC, MJ, KR, VD), pp. 489–494.
DATE-1998-DagaOA: Temperature Effect on Delay for Low Voltage Applications (JMD, EO, DA), pp. 680–685.
EDTC-1997-LuS: A CMOS low-voltage, high-gain op-amp (GNL, GS), pp. 51–55.
DAC-1996-ChandrakasanYVA #design #tool support: Design Considerations and Tools for Low-voltage Digital System Design (AC, IY, CV, DA), pp. 113–118.
EDAC-1994-Sachdev #logic #testing: Transforming Sequential Logic in Digital CMOS ICs for Voltage and IDDQ Testing (MS), pp. 361–365.
DAC-1987-Elias #case study #compilation #generative #layout #re-engineering: A Case Study in Silicon Compilation Software Engineering, HVDEV High Voltage Device Layout Generator (NJE), pp. 82–88.