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Used together with:
substrat (2)
esd (1)
model (1)
circuit (1)
simul (1)

Stem latchup$ (all stems)

1 papers:

DACDAC-1999-LiTRK #modelling #simulation
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (TL, CHT, ER, SMK), pp. 549–554.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.