51 papers:
DAC-2015-LiuZ #configuration management #performance- A reconfigurable analog substrate for highly efficient maximum flow computation (GL, ZZ), p. 6.
DATE-2012-SchoenmakerMSBTJ #scalability #simulation- Large signal simulation of integrated inductors on semi-conducting substrates (WS, MM, BDS, SB, CT, RJ), pp. 1221–1226.
CHI-2012-GarciaTAM #interactive- Interactive paper substrates to support musical creation (JG, TT, CA, WEM), pp. 1825–1828.
DocEng-2011-AdamsPS #case study #forensics #interactive- A study of the interaction of paper substrates on printed forensic imaging (GBA, SBP, SJS), pp. 263–266.
DATE-2010-SrivastavaSB #3d #performance- Efficient 3D high-frequency impedance extraction for general interconnects and inductors above a layered substrate (NS, RS, KB), pp. 459–464.
ASPLOS-2010-EbrahimiLMP #configuration management #manycore #memory management- Fairness via source throttling: a configurable and high-performance fairness substrate for multi-core memory systems (EE, CJL, OM, YNP), pp. 335–346.
SAC-2009-SchippersHH #implementation- An implementation substrate for languages composing modularized crosscutting concerns (HS, MH, RH), pp. 1944–1951.
CASE-2008-KimSEP #component #scalability #self- Large scale self-assembly of crystalline semiconductor microcomponents onto plastic substrates via microfluidic traps (SSK, ES, JRE, BAP), pp. 967–970.
DAC-2008-LiuCJHZDH- Topological routing to maximize routability for package substrate (SL, GC, TTJ, LH, TZ, RD, XH), pp. 566–569.
DATE-2008-SrivastavaSB #multi- High-Frequency Mutual Impedance Extraction of VLSI Interconnects In the Presence of a Multi-layer Conducting Substrate (NS, RS, KB), pp. 426–431.
HPDC-2008-DocanPK #named- DART: a substrate for high speed asynchronous data IO (CD, MP, SK), pp. 219–220.
DAC-2007-LiKBR #flexibility #performance #power management- High Performance and Low Power Electronics on Flexible Substrate (JL, KK, AB, KR), pp. 274–275.
DATE-2007-BronckersSPVR #analysis #interactive #simulation #verification- Interactive presentation: Simulation methodology and experimental verification for the analysis of substrate noise on LC-VCO’s (SB, CS, GVdP, GV, YR), pp. 1520–1525.
DATE-2007-MoselhyHD #3d #performance- pFFT in FastMaxwell: a fast impedance extraction solver for 3D conductor structures over substrate (TM, XH, LD), pp. 1194–1199.
ICPR-v1-2006-ChaoTTJ #detection #fault #using- Defect detection in low-contrast glass substrates using anisotropic diffusion (SMC, DMT, YHT, YRJ), pp. 654–657.
DAC-2005-HuLWD #analysis #integration #novel #using- Analysis of full-wave conductor system impedance over substrate using novel integration techniques (XH, JHL, JW, LD), pp. 147–152.
DAC-2005-XuGFM- A green function-based parasitic extraction method for inhomogeneous substrate layers (CX, RG, TSF, KM), pp. 141–146.
DATE-2005-SoensPWD #analysis #simulation- Simulation Methodology for Analysis of Substrate Noise Impact on Analog / RF Circuits Including Interconnect Resistance (CS, GVdP, PW, SD), pp. 270–275.
DAC-2004-PlasBVDWDGM #simulation- High-level simulation of substrate noise in high-ohmic substrates with interconnect and supply effects (GVdP, MB, GV, PD, PW, SD, GGEG, HDM), pp. 854–859.
DATE-v1-2004-BrandtnerW #named #simulation- SubCALM: A Program for Hierarchical Substrate Coupling Simulation on Floorplan Level (TB, RW), pp. 616–621.
DATE-v1-2004-MurgaiRMHT #analysis #modelling- Sensitivity-Based Modeling and Methodology for Full-Chip Substrate Noise Analysis (RM, SMR, TM, TH, MBT), pp. 610–615.
DATE-v2-2004-ElviraMAG #generative #megamodelling #performance #simulation- A Macromodelling Methodology for Efficient High-Level Simulation of Substrate Noise Generation (LE, FM, XA, JLG), pp. 1362–1363.
DATE-v2-2004-LanD #analysis #modelling #synthesis- Synthesized Compact Models (SCM) of Substrate Noise Coupling Analysis and Synthesis in Mixed-Signal ICs (HL, RWD), pp. 836–843.
DATE-v2-2004-WangMR #automation #megamodelling #predict- Automated, Accurate Macromodelling of Digital Aggressors for Power/Ground/Substrate Noise Prediction (ZW, RM, JSR), pp. 824–829.
DAC-2003-Heydari- Characterizing the effects of clock jitter due to substrate noise in discrete-time D/S modulators (PH), pp. 532–537.
DATE-2003-MartorellMA #evaluation #modelling- Modeling and Evaluation of Substrate Noise Induced by Interconnects (FM, DM, XA), pp. 10524–10529.
DAC-2002-BadarogluTDWMVG #optimisation #reduction #using- Clock tree optimization in synchronous CMOS digital circuits for substrate noise reduction using folding of supply current transients (MB, KT, SD, PW, HDM, IV, GGEG), pp. 399–404.
DAC-2002-KoukabDD #analysis #named #performance- HSpeedEx: a high-speed extractor for substrate noise analysis in complex mixed signal SOC (AK, CD, MJD), pp. 767–770.
DAC-2002-SchrikM #modelling- Combined BEM/FEM substrate resistance modeling (ES, NPvdM), pp. 771–776.
DATE-2002-BrandtnerW #network #power management #simulation- Hierarchical Simulation of Substrate Coupling in Mixed-Signal ICs Considering the Power Supply Network (TB, RW), pp. 1028–1032.
DATE-2002-CathelinSBLC- Substrate Parasitic Extraction for RF Integrated Circuits (AC, DS, DB, YL, FC), p. 1107.
DATE-2002-YmeriNMRSV #approach #parametricity #performance- Simple and Efficient Approach for Shunt Admittance Parameters Calculations of VLSI On-Chip Interconnects on Semiconducting Substrate (HY, BN, KM, DDR, MS, SV), p. 1113.
CAiSE-2002-YangP #component #composition #reuse #web #web service- Web Component: A Substrate for Web Service Reuse and Composition (JY, MPP), pp. 21–36.
DATE-2001-BadarogluHGDMGEB #generative #multi #scalability #simulation- High-level simulation of substrate noise generation from large digital circuits with multiple supplies (MB, MvH, VG, SD, HDM, GGEG, ME, IB), pp. 326–330.
DATE-2001-Fiori- Susceptibility of analog cells to substrate interference (FF), p. 814.
DAC-2000-HeijningenBDEB #generative #power management #simulation- High-level simulation of substrate noise generation including power supply noise coupling (MvH, MB, SD, ME, IB), pp. 446–451.
DAC-2000-KanapkaPW #performance- Fast methods for extraction and sparsification of substrate coupling (JK, JRP, JW), pp. 738–743.
DAC-1999-LiTRK #modelling #simulation- Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (TL, CHT, ER, SMK), pp. 549–554.
DATE-1999-CostaSC #modelling #performance- Efficient Techniques for Accurate Extraction and Modeling of Substrate Coupling in Mixed-Signal IC’s (JPC, LMS, MC), pp. 396–400.
DATE-1999-FeldmanKL #modelling #performance- Efficient Techniques for Modeling Chip-Level Interconnect, Substrate and Package Parasitics (PF, SK, DEL), pp. 418–417.
DAC-1998-ChouW #equation #multi #parametricity- Multilevel Integral Equation Methods for the Extraction of Substrate Coupling Parameters in Mixed-Signal IC’s (MC, JW), pp. 20–25.
DATE-1998-CostaCS #modelling #performance #simulation- Efficient Techniques for Accurate Modeling and Simulation of Substrate Coupling in Mixed-Signal IC’s (JPC, MC, LMS), pp. 892–898.
SOSP-1997-FordBBLLS #kernel #research- The Flux OSKit: A Substrate for Kernel and Language Research (BF, GB, GB, JL, AL, OS), pp. 38–51.
DAC-1996-MiliozziVCMS #design #modelling- Use of Sensitivities and Generalized Substrate Models in Mixed-Signal IC Design (PM, IV, EC, EM, ALSV), pp. 227–232.
DAC-1995-WempleY #analysis #megamodelling #using- Mixed-Signal Switching Noise Analysis Using Voronoi-Tessellated Substrate Macromodels (ILW, ATY), pp. 439–444.
HPDC-1993-BanerjiKTGC #clustering #distributed #memory management- High-Performance Distributed Shared Memory Substrate for Workstation Clusters (AB, DCK, JMT, PMG, DLC), pp. 344–351.
PLDI-1992-JagannathanP #concurrent- A Customizable Substrate for Concurrent Languages (SJ, JP), pp. 55–67.
OOPSLA-1986-SmithDB #design #interface #named #object-oriented- Impulse-86: A Substrate for Object-Oriented Interface Design (RGS, RD, PB), pp. 167–176.
DAC-1977-Christley #design #interactive- Thick film substrate (Micropackage) design utilizing interactive Computer Aided Design systems (FMC), pp. 450–459.
DAC-1977-Waldvogel #hybrid #multi #using- Computer designed multilayer hybrid substrate using thick film technology (CWW), pp. 351–353.
DAC-1970-Farlow #design- Machine aids to the design of ceramic substrates containing integrated circuit chips (CWF), pp. 274–285.