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Used together with:
substrat (2)
model (2)
consid (1)
stack (1)
simul (1)

Stem esd$ (all stems)

2 papers:

DACDAC-2014-KimM #3d #design #on the #reliability
On the Design of Reliable 3D-ICs Considering Charged Device Model ESD Events During Die Stacking (DK, SM), p. 6.
DACDAC-1999-LiTRK #modelling #simulation
Substrate Modeling and Lumped Substrate Resistance Extraction for CMOS ESD/Latchup Circuit Simulation (TL, CHT, ER, SMK), pp. 549–554.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.