5 papers:
DATE-2013-NoguchiNAFAKNMN #energy #hybrid #memory management #performance- D-MRAM cache: enhancing energy efficiency with 3T-1MTJ DRAM/MRAM hybrid memory (HN, KN, KA, SF, EA, KK, TN, SM, HN), pp. 1813–1818.
DAC-2012-MorrisBZP #logic #named #using- mLogic: ultra-low voltage non-volatile logic circuits using STT-MTJ devices (DM, DB, JG(Z, LTP), pp. 486–491.
- DATE-2012-PanagopoulosAR #approach #framework #hybrid #simulation
- A framework for simulating hybrid MTJ/CMOS circuits: Atoms to system approach (GP, CA, KR), pp. 1443–1446.
- DATE-2012-ZhangWLJC #design #symmetry
- Asymmetry of MTJ switching and its implication to STT-RAM designs (YZ, XW, YL, AKJ, YC), pp. 1313–1318.
- DATE-2009-MatsunagaHIMEOH #in memory
- MTJ-based nonvolatile logic-in-memory circuit, future prospects and issues (SM, JH, SI, KM, TE, HO, TH), pp. 433–435.
