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Used together with:
estim (1)
simul (1)
cell (1)
self (1)
circuit (1)

Stem nmos$ (all stems)

3 papers:

DACDAC-1985-KrasniewskiA #estimation #self
Simulation-free estimation of speed degradation in NMOS self-testing circuits for CAD applications (AK, AA), pp. 808–811.
DACDAC-1983-Jouppi #analysis
Timing analysis for nMOS VLSI (NPJ), pp. 411–418.
DACDAC-1982-LuhukayK #layout #synthesis
A layout synthesis system for NMOS gate-cells (JFPL, WJK), pp. 307–314.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.