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Used together with:
simul (1)
static (1)
base (1)
time (1)
transistor (1)

Stem rde$ (all stems)

1 papers:

DACDAC-2010-TangZBM #analysis #simulation #statistics
RDE-based transistor-level gate simulation for statistical static timing analysis (QT, AZ, MB, NvdM), pp. 787–792.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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