Used together with:
vhdl
(1)
diagnosi
(1)
verif
(1)
system
(1)
Stem
vvds$ (
all stems
)
1 papers:
DAC-1989-LiawTL
#named
#verification
VVDS: A Verification/Diagnosis System for VHDL (
HTL
,
KTT
,
CSL
), pp. 435–440.
Bibliography of Software Language Engineering in Generated Hypertext
(
BibSLEIGH
) is created and maintained by
Dr. Vadim Zaytsev
.
Hosted as a part of
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on
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.