BibSLEIGH — Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits

V. Vasudevan
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
DAC, 2005.

DAC 2005

@inproceedings{DAC-2005-Vasudevan,
	author        = "V. Vasudevan",
	booktitle     = "{Proceedings of the 42nd Design Automation Conference}",
	doi           = "10.1145/1065579.1065685",
	isbn          = "1-59593-058-2",
	pages         = "397--402",
	publisher     = "{ACM}",
	title         = "{Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits}",
	year          = 2005,
}

V. VasudevanSimulation of the effects of timing jitter in track-and-hold and sample-and-hold circuitsDAC, 2005.

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V. Vasudevan
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits
DAC, 2005.