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Travelled to:
1 × Germany
2 × USA
Collaborated with:
S.Ramprasath M.Vijaykumar ∅
Talks about:
time (3) statist (2) hold (2) algorithm (1) circuit (1) analysi (1) static (1) normal (1) jitter (1) effici (1)

Person: V. Vasudevan

DBLP DBLP: Vasudevan:V=

Contributed to:

DAC 20152015
DATE 20142014
DAC 20052005

Wrote 3 papers:

DAC-2015-RamprasathV #algorithm #optimisation #performance #statistics
An efficient algorithm for statistical timing yield optimization (SR, VV), p. 6.
DATE-2014-VijaykumarV #analysis #canonical #statistics #using
Statistical static timing analysis using a skew-normal canonical delay model (MV, VV), pp. 1–6.
DAC-2005-Vasudevan #simulation
Simulation of the effects of timing jitter in track-and-hold and sample-and-hold circuits (VV), pp. 397–402.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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