Jovanka Ciric, Gin Yee, Carl Sechen
Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic
DATE, 2000.
@inproceedings{DATE-2000-CiricYS,
author = "Jovanka Ciric and Gin Yee and Carl Sechen",
booktitle = "{Proceedings of the Fifth Conference on Design, Automation and Test in Europe}",
doi = "10.1109/DATE.2000.840284",
isbn = "0-7695-0537-6",
pages = "277--282",
publisher = "{IEEE Computer Society}",
title = "{Delay Minimization and Technology Mapping of Two-Level Structures and Implementation Using Clock-Delayed Domino Logic}",
year = 2000,
}