Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
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Balakrishna Kumthekar, Fabio Somenzi
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs
DATE, 2000.

DATE 2000
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@inproceedings{DATE-2000-KumthekarS,
	author        = "Balakrishna Kumthekar and Fabio Somenzi",
	booktitle     = "{Proceedings of the Fifth Conference on Design, Automation and Test in Europe}",
	doi           = "10.1109/DATE.2000.840039",
	isbn          = "0-7695-0537-6",
	pages         = "202--207",
	publisher     = "{IEEE Computer Society}",
	title         = "{Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs}",
	year          = 2000,
}

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