BibSLEIGH corpus
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Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
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Travelled to:
1 × France
1 × USA
Collaborated with:
F.Somenzi L.Benini E.Macii
Talks about:
power (2) optim (2) fpgas (2) placement (1) simultan (1) reduct (1) place (1) logic (1) delay (1) base (1)

Person: Balakrishna Kumthekar

DBLP DBLP: Kumthekar:Balakrishna

Contributed to:

DATE 20002000
DAC 19981998

Wrote 2 papers:

DATE-2000-KumthekarS #logic #optimisation #reduction
Power and Delay Reduction via Simultaneous Logic and Placement Optimization in FPGAs (BK, FS), pp. 202–207.
DAC-1998-KumthekarBMS #optimisation
In-Place Power Optimization for LUT-Based FPGAs (BK, LB, EM, FS), pp. 718–721.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.