BibSLEIGH — A clock-gating based capture power droop reduction methodology for at-speed scan testing

Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu
A clock-gating based capture power droop reduction methodology for at-speed scan testing
DATE, 2011.

DATE 2011

@inproceedings{DATE-2011-YangSSL,
	author        = "Bo Yang and Amit Sanghani and Shantanu Sarangi and Chunsheng Liu",
	booktitle     = "{Proceedings of the 15th Conference on Design, Automation and Test in Europe}",
	isbn          = "978-1-61284-208-0",
	pages         = "197--203",
	publisher     = "{IEEE}",
	title         = "{A clock-gating based capture power droop reduction methodology for at-speed scan testing}",
	year          = 2011,
}

Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng LiuA clock-gating based capture power droop reduction methodology for at-speed scan testingDATE, 2011.

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Bo Yang, Amit Sanghani, Shantanu Sarangi, Chunsheng Liu
A clock-gating based capture power droop reduction methodology for at-speed scan testing
DATE, 2011.