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Travelled to:
1 × France
Collaborated with:
B.Yang S.Sarangi C.Liu
Talks about:
methodolog (1) reduct (1) captur (1) speed (1) power (1) droop (1) clock (1) test (1) scan (1) gate (1)

Person: Amit Sanghani

DBLP DBLP: Sanghani:Amit

Contributed to:

DATE 20112011

Wrote 1 papers:

DATE-2011-YangSSL #reduction #testing
A clock-gating based capture power droop reduction methodology for at-speed scan testing (BY, AS, SS, CL), pp. 197–203.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
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