BibSLEIGH — A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation

Kris Tiri, Ingrid Verbauwhede
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
DATE, 2004.

DATE v1 2004

@inproceedings{DATE-v1-2004-TiriV,
	author        = "Kris Tiri and Ingrid Verbauwhede",
	booktitle     = "{Proceedings of the Eighth Conference on Design, Automation and Test in Europe, Volume 1}",
	doi           = "10.1109/DATE.2004.1268856",
	isbn          = "0-7695-2085-5",
	pages         = "246--251",
	publisher     = "{IEEE Computer Society}",
	title         = "{A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation}",
	year          = 2004,
}

Kris Tiri, Ingrid VerbauwhedeA Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA ImplementationDATE, 2004.

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Kris Tiri, Ingrid Verbauwhede
A Logic Level Design Methodology for a Secure DPA Resistant ASIC or FPGA Implementation
DATE, 2004.