Shlomo Weiss
Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors
HPCA, 1995.
@inproceedings{HPCA-1995-Weiss,
author = "Shlomo Weiss",
booktitle = "{Proceedings of the First Symposium on High-Performance Computer Architecture}",
doi = "10.1109/HPCA.1995.386559",
isbn = "0-8186-6445-2",
pages = "14--21",
publisher = "{IEEE Computer Society}",
title = "{Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors}",
year = 1995,
}











