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Travelled to:
4 × USA
Collaborated with:
R.H.Katz J.E.Smith K.Rotzell T.Rhyne A.Goldfein
Talks about:
pipelin (2) design (2) superscalar (1) supercomput (1) processor (1) interlock (1) implement (1) transact (1) techniqu (1) parallel (1)

Person: Shlomo Weiss

DBLP DBLP: Weiss:Shlomo

Contributed to:

HPCA 19951995
ASPLOS 19871987
DAC 19861986
DAC 19841984
DAC 19831983

Wrote 5 papers:

HPCA-1995-Weiss #implementation #multi #queue
Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors (SW), pp. 14–21.
ASPLOS-1987-WeissS #case study #compilation #pipes and filters
A Study of Scalar Compilation Techniques for Pipelined Supercomputers (SW, JES), pp. 105–109.
DAC-1986-WeissRRG #design #named
DOSS: a storage system for design data (SW, KR, TR, AG), pp. 41–47.
DAC-1984-KatzW #design #transaction
Design transaction management (RHK, SW), pp. 692–693.
DAC-1983-KatzW #concept
Chip assemblers: Concepts and capabilities (RHK, SW), pp. 25–30.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.