Stem regist$ (all stems)

252 papers:

DAC-2015-ChiangCLJ #design #power management #scalability

Scalable sequence-constrained retention register minimization in power gating design (TWC, KHC, YTL, JHRJ), p. 6.

DAC-2015-IsmailLS #performance #worst-case

Improving worst-case cache performance through selective bypassing and register-indexed cache (MI, DL, GES), p. 6.

DAC-2015-LiCSHLWY #hybrid #power management

A STT-RAM-based low-power hybrid register file for GPGPUs (GL, XC, GS, HH, YL, YW, HY), p. 6.

DATE-2015-JoostenS #architecture #automation #communication #design #modelling

Automatic extraction of micro-architectural models of communication fabrics from register transfer level designs (SJCJ, JS), pp. 1413–1418.

DATE-2015-TanLF #memory management #reliability #using

Soft-error reliability and power co-optimization for GPGPUS register file using resistive memory (JT, ZL, XF), pp. 369–374.

DATE-2015-ZhaoLXLHX #cyber-physical #energy #reduction

Software assisted non-volatile register reduction for energy harvesting based cyber-physical system (MZ, QL, MX, YL, JH, CJX), pp. 567–572.

CSL-2015-MazowieckiR #automaton #logic #towards

Maximal Partition Logic: Towards a Logical Characterization of Copyless Cost Register Automata (FM, CR), pp. 144–159.

LICS-2015-MurawskiRT #automaton #similarity

Bisimilarity in Fresh-Register Automata (ASM, SJR, NT), pp. 156–167.

DAC-2014-ChenT #control flow #design

Reliability-aware Register Binding for Control-Flow Intensive Designs (LC, MBT), p. 6.

DAC-2014-MaoWZCL #architecture #memory management #using

Exploration of GPGPU Register File Architecture Using Domain-wall-shift-write based Racetrack Memory (MM, WW, YZ, YC, HHL), p. 6.

DATE-2014-ZhangWSX #clustering

Lifetime holes aware register allocation for clustered VLIW processors (XZ, HW, HS, JX), pp. 1–4.

HPCA-2014-LakshminarayanaK #algorithm #graph

Spare register aware prefetching for graph algorithms on GPUs (NBL, HK), pp. 614–625.

DAC-2013-HamzehSV #architecture #configuration management #named

REGIMap: register-aware application mapping on coarse-grained reconfigurable architectures (CGRAs) (MH, AS, SBKV), p. 10.

DATE-2013-CarreteroHMRV

Capturing vulnerability variations for register files (JC, EH, MM, TR, XV), pp. 1468–1473.

DATE-2013-CastellanaF #analysis #independence #liveness #scheduling #synthesis

Scheduling independent liveness analysis for register binding in high level synthesis (VGC, FF), pp. 1571–1574.

FoSSaCS-2013-TzevelekosG #automaton

History-Register Automata (NT, RG), pp. 17–33.

TACAS-2013-GrigoreDPT #automaton #runtime #verification

Runtime Verification Based on Register Automata (RG, DD, RLP, NT), pp. 260–276.

DLT-2013-BolligHLM #approach #automaton #learning

A Fresh Approach to Learning Register Automata (BB, PH, ML, BM), pp. 118–130.

CC-2013-Krause #polynomial

Optimal Register Allocation in Polynomial Time (PKK), pp. 1–20.

HPCA-2013-Abdel-MajeedA #performance

Warped register file: A power efficient register file for GPGPUs (MAM, MA), pp. 412–423.

LICS-2013-AlurDDRY #automaton

Regular Functions and Cost Register Automata (RA, LD, JVD, MR, YY), pp. 13–22.

DAC-2012-DonkohLS #adaptation #design #hybrid #predict #using

A hybrid and adaptive model for predicting register file and SRAM power using a reference design (ED, AL, ES), pp. 62–67.

DATE-2012-SabenaRS #algorithm #testing

A new SBST algorithm for testing the register file of VLIW processors (DS, MSR, LS), pp. 412–417.

DATE-2012-SheHMC #architecture #energy #scheduling

Scheduling for register file energy minimization in explicit datapath architectures (DS, YH, BM, HC), pp. 388–393.

DATE-2012-TabkhiS #approach #power management

Application-specific power-efficient approach for reducing register file vulnerability (HT, GS), pp. 574–577.

DATE-2012-WangJZD #design #power management

Low power aging-aware register file design by duty cycle balancing (SW, TJ, CZ, GD), pp. 546–549.

TACAS-2012-MertenHSCJ #automaton #learning

Demonstrating Learning of Register Automata (MM, FH, BS, SC, BJ), pp. 466–471.

IFM-2012-DiaconescuLPSS #interactive

Refinement-Preserving Translation from Event-B to Register-Voice Interactive Systems (DD, IL, LP, KS, GS), pp. 221–236.

HPCA-2012-BattleHHR #flexibility #using

Flexible register management using reference counting (SJB, ADH, MH, AR), pp. 273–284.

LCTES-2012-HuangZX #architecture #clustering #embedded #realtime

WCET-aware re-scheduling register allocation for real-time embedded systems with clustered VLIW architecture (YH, MZ, CJX), pp. 31–40.

VMCAI-2012-HowarSJC #automaton #canonical

Inferring Canonical Register Automata (FH, BS, BJ, SC), pp. 251–266.

DATE-2011-ChungCCK

Formal reset recovery slack calculation at the register transfer level (CNC, CWC, KHC, SYK), pp. 571–574.

DATE-2011-LiuOXL #energy #reduction

Register allocation for simultaneous reduction of energy and peak temperature on registers (TL, AO, CJX, ML), pp. 20–25.

DocEng-2011-Brailsford #automation #layout

Automated conversion of web-based marriage register data into a printed format with predefined layout (DFB), pp. 61–64.

ICDAR-2011-RomeroSSV #recognition

Handwritten Text Recognition for Marriage Register Books (VR, JAS, NS, EV), pp. 533–537.

LATA-2011-LisitsaPS #automaton

Planarity of Knots, Register Automata and LogSpace Computability (AL, IP, RS), pp. 366–377.

POPL-2011-Tzevelekos #automaton

Fresh-register automata (NT), pp. 295–306.

SAC-2011-TianXLC #optimisation #order

Loop fusion and reordering for register file optimization on stream processors (WT, CJX, ML, EC), pp. 560–565.

CC-2011-BuchwaldZB

SSA-Based Register Allocation with PBQP (SB, AZ, TB), pp. 42–61.

CGO-2011-LiWH #stack

Dynamic register promotion of stack variables (JL, CW, WCH), pp. 21–31.

CASE-2010-ChoiTGLNJK #algorithm #web

Web register control algorithm for roll-to-roll system based printed electronics (KHC, TTT, PG, KHL, MNN, JDJ, DSK), pp. 867–872.

DATE-2010-AbellaCCV

The split register file (JA, JC, PC, XV), pp. 945–948.

DATE-2010-WongAN #configuration management

Dynamically reconfigurable register file for a softcore VLIW processor (SW, FA, FN), pp. 969–972.

DRR-2010-KnoblockCCGMS #approach

A general approach to discovering, registering, and extracting features from raster maps (CAK, CCC, YYC, AG, MM, CS), pp. 1–10.

ESOP-2010-BlazyRA #graph #verification

Formal Verification of Coalescing Graph-Coloring Register Allocation (SB, BR, AWA), pp. 145–164.

SAC-2010-KimJJ

Dynamic register-renaming scheme for reducing power-density and temperature (JK, STJ, CSJ), pp. 231–237.

CC-2010-BraunMH

Preference-Guided Register Assignment (MB, CM, SH), pp. 205–223.

CC-2010-Hoflehner

Strategies for Predicate-Aware Register Allocation (GH), pp. 185–204.

CC-2010-RideauL #validation

Validating Register Allocation and Spilling (SR, XL), pp. 224–243.

CGO-2010-KochBF #code generation

Integrated instruction selection and register allocation for compact code generation exploiting freeform mixing of 16- and 32-bit instructions (TJKEvK, IB, BF), pp. 180–189.

CGO-2010-OdairaNIKN #graph

Coloring-based coalescing for graph coloring register allocation (RO, TN, TI, HK, TN), pp. 160–169.

CGO-2010-WimmerF #linear

Linear scan register allocation on SSA form (CW, MF), pp. 170–179.

DAC-2009-ChouCK #synthesis

Handling don’t-care conditions in high-level synthesis and application for reducing initialized registers (HZC, KHC, SYK), pp. 412–415.

DAC-2009-Falk #graph

WCET-aware register allocation based on graph coloring (HF), pp. 726–731.

DAC-2009-ShinPS #synthesis #using

Register allocation for high-level synthesis using dual supply voltages (IS, SP, YS), pp. 937–942.

DATE-2009-ChiangOY

Register placement for high-performance circuits (MFC, TO, TY), pp. 1470–1475.

DATE-2009-LeeS #fault #static analysis

Static analysis to mitigate soft errors in register files (JL, AS), pp. 1367–1372.

DATE-2009-MohammadZadehMJZ #multi #network

Multi-domain clock skew scheduling-aware register placement to optimize clock distribution network (NM, MM, AJ, MSZ), pp. 833–838.

DATE-2009-WangHZC #design

Exploiting narrow-width values for thermal-aware register file designs (SW, JSH, SGZ, SWC), pp. 1422–1427.

DocEng-2009-Brailsford #automation

Automated re-typesetting, indexing and contentenhancement for scanned marriage registers (DFB), pp. 29–38.

CC-2009-BraunH #source code

Register Spilling and Live-Range Splitting for SSA-Form Programs (MB, SH), pp. 174–189.

CC-2009-PereiraP

SSA Elimination after Register Allocation (FMQP, JP), pp. 158–173.

CGO-2009-Baev

Techniques for Region-Based Register Allocation (IDB), pp. 147–156.

LCTES-2009-LeeS #compilation #fault #optimisation

A compiler optimization to reduce soft errors in register files (JL, AS), pp. 41–49.

PPoPP-2009-YangWXDZ #graph #optimisation

Comparability graph coloring for optimizing utilization of stream register files in stream processors (XY, LW, JX, YD, YZ), pp. 111–120.

DAC-2008-HomayounPMV #embedded #energy #performance #scalability

Dynamic register file resizing and frequency scaling to improve embedded processor performance and energy-delay efficiency (HH, SP, MAM, AVV), pp. 68–71.

DAC-2008-HurstMB #constraints #scalability

Scalable min-register retiming under timing and initializability constraints (APH, AM, RKB), pp. 534–539.

DAC-2008-ZhouYP #compilation #reduction

Compiler-driven register re-assignment for register file power-density and temperature reduction (XZ, CY, PP), pp. 750–753.

DATE-2008-CongX #network

Simultaneous FU and Register Binding Based on Network Flow Method (JC, JX), pp. 1057–1062.

DATE-2008-DubrovaTT #analysis #feedback #on the #synthesis

On Analysis and Synthesis of (n, k)-Non-Linear Feedback Shift Registers (ED, MT, HT), pp. 1286–1291.

DATE-2008-XueSSQ #clustering #constraints #effectiveness #memory management #scheduling

Effective Loop Partitioning and Scheduling under Memory and Register Dual Constraints (CJX, EHMS, ZS, MQ), pp. 1202–1207.

PLDI-2008-PereiraP

Register allocation by puzzle solving (FMQP, JP), pp. 216–226.

ICPR-2008-SwadzbaVHW

Reducing noise and redundancy in registered range data for planar surface extraction (AS, ALV, MH, SW), pp. 1–4.

LCTES-2008-BachirTC

Post-pass periodic register allocation to minimise loop unrolling degree (MB, SAAT, AC), pp. 141–150.

LCTES-2008-SutterCAM #array #configuration management

Placement-and-routing-based register allocation for coarse-grained reconfigurable arrays (BDS, PC, TVA, BM), pp. 151–160.

VMCAI-2008-Palsberg #verification

Verification of Register Allocators (JP), p. 6.

DAC-2007-IwataYF

A DFT Method for Time Expansion Model at Register Transfer Level (HI, TY, HF), pp. 682–687.

DAC-2007-LimKK #architecture #communication #distributed #synthesis

Interconnect and Communication Synthesis for Distributed Register-File Microarchitecture (KHL, YK, TK), pp. 765–770.

DATE-2007-ParkPBBKD #architecture #embedded #performance #pointer

Register pointer architecture for efficient embedded processors (JP, SBP, JDB, DBS, CK, WJD), pp. 600–605.

DATE-2007-RaghavanLJCVC #embedded #power management #symmetry

Very wide register: an asymmetric register file organization for low power embedded processors (PR, AL, MJ, FC, DV, HC), pp. 1066–1071.

DATE-2007-SafarSES #configuration management #interactive #satisfiability

Interactive presentation: A shift register based clause evaluator for reconfigurable SAT solver (MS, MS, MWEK, AS), pp. 153–158.

SAS-2007-NandivadaPP #evaluation #framework #verification

A Framework for End-to-End Verification and Evaluation of Register Allocators (VKN, FMQP, JP), pp. 153–169.

ICALP-2007-LeePP #alias #source code

Aliased Register Allocation for Straight-Line Programs Is NP-Complete (JKL, JP, FMQP), pp. 680–691.

CC-2007-NagarakatteG #integer #linear #pipes and filters #programming #scheduling #using

Register Allocation and Optimal Spill Code Scheduling in Software Pipelined Loops Using 0-1 Integer Linear Programming Formulation (SGN, RG), pp. 126–140.

CC-2007-SarkarB #linear

Extended Linear Scan: An Alternate Foundation for Global Register Allocation (VS, RB), pp. 141–155.

CGO-2007-BouchezDR #complexity #on the

On the Complexity of Register Coalescing (FB, AD, FR), pp. 102–114.

LCTES-2007-AhnLP #architecture

Optimistic coalescing for heterogeneous register architectures (MA, JL, YP), pp. 93–102.

LCTES-2007-ChenTCLYLL #compilation #distributed #embedded

Enabling compiler flow for embedded VLIW DSP processors with distributed register files (CKC, LHT, SCC, YJL, YPY, CHL, JKL), pp. 146–148.

LCTES-2007-HinesTW #using

Addressing instruction fetch bottlenecks by using an instruction register file (SRH, GST, DBW), pp. 165–174.

LCTES-2007-XuT #named

Tetris: a new register pressure control technique for VLIW processors (WX, RT), pp. 113–122.

ICLP-2007-Zhou #prolog

A Register-Free Abstract Prolog Machine with Jumbo Instructions (NFZ), pp. 455–457.

DAC-2006-HuangCNY

Register binding for clock period minimization (SHH, CHC, YTN, WCY), pp. 439–444.

FoSSaCS-2006-PereiraP

Register Allocation After Classical SSA Elimination is NP-Complete (FMQP, JP), pp. 79–93.

PLDI-2006-KoesG

A global progressive register allocator (DRK, SCG), pp. 204–215.

SAS-2006-HuangCS #debugging #identification

Catching and Identifying Bugs in Register Allocation (YH, BRC, MLS), pp. 281–300.

ICPR-v4-2006-ZhouL06a #image #integration #multi

Flag Guided Integration of Multiple Registered Range Images (HZ, YL), pp. 17–20.

CC-2006-BarikS

Enhanced Bitwidth-Aware Register Allocation (RB, VS), pp. 263–276.

CC-2006-HackGG #source code

Register Allocation for Programs in SSA-Form (SH, DG, GG), pp. 247–262.

CC-2006-NandivadaP #named #stack

SARA: Combining Stack Allocation and Register Allocation (VKN, JP), pp. 232–246.

CGO-2006-CooperD #compilation #graph #runtime

Tailoring Graph-coloring Register Allocation For Runtime Compilation (KDC, AD), pp. 39–49.

CGO-2006-LupoW #optimisation

Post Register Allocation Spill Code Optimization (CL, KDW), pp. 245–255.

LCTES-2006-ParkSDNPE #reduction #scheduling

Bypass aware instruction scheduling for register file power reduction (SP, AS, NDD, AN, YP, EE), pp. 173–181.

LICS-2006-DemriL #automaton #ltl #quantifier

LTL with the Freeze Quantifier and Register Automata (SD, RL), pp. 17–26.

DAC-2005-LuSHZCHH #navigation #network

Navigating registers in placement for clock network minimization (YL, CCNS, XH, QZ, YC, LH, JH), pp. 176–181.

DATE-2005-BaradaranD #algorithm #architecture #configuration management

A Register Allocation Algorithm in the Presence of Scalar Replacement for Fine-Grain Configurable Architectures (NB, PCD), pp. 6–11.

DATE-2005-MemikKO #fault

Increasing Register File Immunity to Transient Errors (GM, MTK, ÖÖ), pp. 586–591.

TACAS-2005-JainIGG #abstraction #locality

Localization and Register Sharing for Predicate Abstraction (HJ, FI, AG, MKG), pp. 397–412.

PLDI-2005-RongDG #multi #pipes and filters

Register allocation for software pipelined multi-dimensional loops (HR, AD, GRG), pp. 154–167.

PLDI-2005-ZhuangP #difference

Differential register allocation (XZ, SP), pp. 168–179.

CGO-2005-KoesG #architecture

A Progressive Register Allocator for Irregular Architectures (DK, SCG), pp. 269–280.

HPCA-2005-KondoN #clustering #performance #power management

A Small, Fast and Low-Power Register File by Bit-Partitioning (MK, HN), pp. 40–49.

DAC-2004-NakamuraHKYY #c #c++ #communication #hardware #performance #using

A fast hardware/software co-verification method for system-on-a-chip by using a C/C++ simulator and FPGA emulator with shared register communication (YN, KH, IK, KY, TY), pp. 299–304.

DAC-2004-ShehataA #composition #verification

A general decomposition strategy for verifying register renaming (HIS, MA), pp. 234–237.

DATE-v2-2004-LeiningerGM #configuration management

Diagnosis of Scan-Chains by Use of a Configurable Signature Register and Error-Correcting Code (AL, MG, PM), pp. 1302–1309.

PLDI-2004-SmithRH #algorithm #graph

A generalized algorithm for graph-coloring register allocation (MDS, NR, GHH), pp. 277–288.

PLDI-2004-ZhuangP #network #parallel #thread

Balancing register allocation across threads for a multithreaded network processor (XZ, SP), pp. 289–300.

ICPR-v3-2004-LangsRRC #3d #modelling #visualisation

Building and Registering Parameterized 3D Models of Vessel Trees for Visualization during Intervention (GL, PR, DR, FC), pp. 726–729.

ICPR-v4-2004-IrfanogluGA #3d #automation #recognition #using

3D Shape-based Face Recognition using Automatically Registered Facial Surfaces (MOI, BG, LA), pp. 183–186.

HPCA-2004-JayasenaEAD

Stream Register Files with Indexed Access (NJ, ME, JHA, WJD), pp. 60–72.

HPCA-2004-PengPL #performance

Signature Buffer: Bridging Performance Gap between Registers and Caches (LP, JKP, KL), pp. 164–175.

LCTES-2004-DaveauTLS #embedded #framework

A retargetable register allocation framework for embedded processors (JMD, TT, TL, MS), pp. 202–210.

LCTES-2004-ZhuangZP #embedded

Hardware-managed register allocation for embedded processors (XZ, TZ, SP), pp. 192–201.

DRR-2003-MaderlechnerS #recognition #set #using

Extraction of valid data sets in registers using recognition of invalidation lines (GM, PS), pp. 67–72.

ICDAR-2003-KameyaMO #online #sequence #verification

Figure-Based Writer Verification by Matching between an Arbitrary Part of Registered Sequence and an Input Sequence Extracted from On-Line Handwritten Figures (HK, SM, RO), pp. 985–989.

ESOP-2003-Ohori #proving

Register Allocation by Proof Transformation (AO), pp. 399–413.

POPL-2003-TallamG

Bitwidth aware global register allocation (ST, RG), pp. 85–96.

LDTA-2003-Lee #framework

A Formally Verified Register Allocation Framework (KL), pp. 515–531.

CC-2003-Andersson #graph

Register Allocation by Optimal Graph Coloring (CA), pp. 33–45.

CC-2003-JohnsonM #dependence #graph #using

Combined Code Motion and Register Allocation Using the Value State Dependence Graph (NJ, AM), pp. 1–16.

CC-2003-KandemirICR

Address Register Assignment for Reducing Code Size (MTK, MJI, GC, JR), pp. 273–289.

CC-2003-TouatiE #pipes and filters

Early Control of Register Pressure for Software Pipelined Loops (SAAT, CE), pp. 17–32.

CGO-2003-LinCHY #using

Speculative Register Promotion Using Advanced Load Address Table (ALAT) (JL, TC, WCH, PCY), pp. 125–134.

CGO-2003-SettleCHL #architecture #optimisation #stack

Optimization for the Intel® Itanium ®Architectur Register Stack (AS, DAC, GH, DML), pp. 115–124.

WCRE-2002-ProbstKS #analysis #liveness #optimisation

Register Liveness Analysis for Optimizing Dynamic Binary Translation (MP, AK, BS), pp. 35–44.

ICPR-v4-2002-AppelN #3d #framework #image #re-engineering

3D Reconstruction from Co-Registered Orthographic and Perspective Images: Theoretical Framework and Applications (MA, NN), pp. 21–26.

ICPR-v4-2002-WangTSHNY #image

Registering Panoramic Range Data and Omni-directional Color Image Based on Edge Histograms (CW, HT, YS, HH, YN, KY), pp. 355–358.

PADL-2002-JohanssonS #compilation #erlang #linear

Linear Scan Register Allocation in a High-Performance Erlang Compiler (EJ, KFS), pp. 101–119.

SAC-2002-GarigipatiN #profiling

Evaluating the use of profiling by a region-based register allocator (KVG, CN), pp. 953–957.

CC-2002-CilioC #using

Global Variable Promotion: Using Registers to Reduce Cache Power Dissipation (AGMC, HC), pp. 247–260.

CC-2002-MossenbockP #constraints #linear

Linear Scan Register Allocation in the Context of SSA Form and Register Constraints (HM, MP), pp. 229–246.

HPCA-2002-BrownP #pipes and filters #using

Using Internal Redundant Representations and Limited Bypass to Support Pipelined Adders and Register Files (MDB, YNP), pp. 289–298.

LCTES-SCOPES-2002-Barthelmann #operating system

Inter-task register-allocation for static operating systems (VB), pp. 149–154.

LCTES-SCOPES-2002-ChoPW #algorithm #architecture #graph #memory management #performance

Efficient register and memory assignment for non-orthogonal architectures via graph coloring and MST algorithms (JC, YP, DBW), pp. 130–138.

LCTES-SCOPES-2002-ScholzE #architecture

Register allocation for irregular architectures (BS, EE), pp. 139–148.

DAC-2001-OckunzziP #algorithm

Test Strategies for BIST at the Algorithmic and Register-Transfer Levels (KAO, CAP), pp. 65–70.

DATE-2001-RoussellePBMV #embedded #fault

A register-transfer-level fault simulator for permanent and transient faults in embedded processors (CR, MP, AB, TM, HTV), p. 811.

ICDAR-2001-FeldbachT #detection #segmentation

Line Detection and Segmentation in Historical Church Registers (MF, KDT), pp. 743–747.

PLDI-2001-AppelG

Optimal Spilling for CISC Machines with Few Registers (AWA, LG), pp. 243–253.

SAC-2001-AltemoseN #pipes and filters

Register pressure responsive software pipelining (GA, CN), pp. 626–631.

CC-2001-OttoniRARM #embedded #source code

Optimal Live Range Merge for Address Register Allocation in Embedded Programs (GO, SR, GA, SR, SM), pp. 274–288.

CC-2001-Touati

Register Saturation in Superscalar and VLIW Codes (SAAT), pp. 213–228.

HPCA-2001-WangWKRS #execution #scheduling

Register Renaming and Scheduling for Dynamic Execution of Predicated Code (PHW, HW, RMK, KR, JPS), pp. 15–25.

LCTES-OM-2001-HuangCS #architecture

Loop Transformations for Architectures with Partitioned Register Banks (XH, SC, PHS), pp. 48–55.

LCTES-OM-2001-ParkLM

Register Allocation for Banked Register File (JP, JHL, SMM), pp. 39–47.

DATE-2000-SchonherrS #algorithm #automation #equivalence

Automatic Equivalence Check of Circuit Descriptions at Clocked Algorithmic and Register Transfer Level (JS, BS), p. 759.

ICPR-v1-2000-DionLB #2d #3d #image #sequence

3D Triangular Mesh Matching through a Sequence of Registered 2D and 3D Images (DDJ, DL, LB), pp. 1977–1980.

SAC-2000-KreahlingN

Profile Assisted Register Allocation (WCK, CN), pp. 774–781.

SAC-2000-ShrewsburyN #impact analysis

Reducing the Impact of Software Prefetching on Register Pressure (DWS, CN), pp. 767–773.

HPCA-2000-RixnerDKMKO

Register Organization for Media Processing (SR, WJD, BK, PRM, UJK, JDO), pp. 375–386.

LCTES-2000-BairagiPA #embedded #framework #quality #set

A Framework for Enhancing Code Quality in Limited Register Set Embedded Processors (DB, SP, DPA), pp. 81–95.

DATE-1999-EcklL #multi

Retiming Sequential Circuits with Multiple Register Classes (KE, CL), p. 650–?.

DATE-1999-KallaC #equivalence #performance

Performance Driven Resynthesis by Exploiting Retiming-Induced State Register Equivalence (PK, MJC), pp. 638–642.

DATE-1999-MansouriV #design #verification

Accounting for Various Register Allocation Schemes During Post-Synthesis Verification of RTL Designs (NM, RV), p. 223–?.

CC-1999-GuptaB

Register Pressure Sensitive Redundancy Elimination (RG, RB), pp. 107–121.

CC-1999-LiberatoreFK #algorithm #evaluation

Evaluation of Algorithms for Local Register Allocation (VL, MFC, UK), pp. 137–152.

DATE-1998-BasuLM #source code

Register-Constrained Address Computation in DSP Programs (AB, RL, PM), pp. 929–930.

DATE-1998-MesmanSTMJ #approach #constraints #pipes and filters

A Constraint Driven Approach to Loop Pipelining and Register Binding (BM, MTJS, AHT, JLvM, JAGJ), pp. 377–383.

DATE-1998-Mutz #modelling

Register Transfer Level VHDL Models without Clocks (MM), pp. 153–158.

PLDI-1998-ChowKLLT

Register Promotion by Partial Redundancy Elimination of Loads and Stores (FCC, RK, SML, RL, PT), pp. 26–37.

PLDI-1998-SastryJ #algorithm

A New Algorithm for Scalar Register Promotion based on SSA Form (AVSS, RDCJ), pp. 15–25.

PLDI-1998-TraubHS #quality

Quality and Speed in Linear-scan Register Allocation (OT, GHH, MDS), pp. 142–151.

CC-1998-CooperS #graph

Live Range Splitting in a Graph Coloring Register Allocator (KDC, LTS), pp. 174–187.

CC-1998-LelaitGE #algorithm #performance

A New Fast Algorithm for Optimal Register Allocation in Modulo Scheduled Loops (SL, GRG, CE), pp. 204–218.

HPCA-1998-GonzalezGV

Virtual-Physical Registers (AG, JG, MV), pp. 175–184.

HPCA-1998-JimenezLF #evaluation #performance

Performance Evaluation of Tiling for the Register Level (MJ, JML, AF), pp. 254–265.

DAC-1997-Gebotys #energy #memory management #network #using

Low Energy Memory and Register Allocation Using Network Flow (CHG), pp. 435–440.

EDTC-1997-HerrmannE #synthesis

Register synthesis for speculative computation (DH, RE), pp. 463–467.

PLDI-1997-CooperL #c #source code

Register Promotion in C Programs (KDC, JL), pp. 308–319.

PLDI-1997-LuehG

Call-Cost Directed Register Allocation (GYL, TRG), pp. 296–307.

IFL-1997-Agat

Types for Register Allocation (JA), pp. 92–111.

DAC-1996-AraujoML #architecture #code generation #using

Using Register-Transfer Paths in Code Generation for Heterogeneous Memory-Register Architectures (GA, SM, MTCL), pp. 591–596.

DAC-1996-ErcanliP #scheduling #synthesis

A Register File and Scheduling Model for Application Specific Processor Synthesis (EE, CAP), pp. 35–40.

DAC-1996-RaghunathanDJ #analysis #reduction

Glitch Analysis and Reduction in Register Transfer Level (AR, SD, NKJ), pp. 331–336.

PLILP-1996-Kessler #graph #scheduling

Scheduling Expression DAGs for Minimal Register Need (CWK), pp. 228–242.

POPL-1996-GeorgeA

Iterated Register Coalescing (LG, AWA), pp. 208–218.

POPL-1996-KurlanderF #interprocedural

Minimum Cost Interprocedural Register Allocation (SMK, CNF), pp. 230–241.

HPCA-1996-FarkasJC #design

Register File Design Considerations in Dynamically Scheduled Processors (KIF, NPJ, PC), pp. 40–51.

JICSLP-1996-Neumerkel #interprocedural #text-to-text

Interprocedural Register Allocation for the WAM based on Source to Source Transformations (UN), pp. 127–141.

DAC-1995-ChangP #power management

Register Allocation and Binding for Low Power (JMC, MP), pp. 29–35.

DAC-1995-FrankRS #architecture

Constrained Register Allocation in Bus Architectures (EF, SR, MS), pp. 170–175.

DAC-1995-WuL

Register Minimization beyond Sharing among Variables (TYW, YLL), pp. 164–169.

PLDI-1995-BurgerWD #lazy evaluation #using

Register Allocation Using Lazy Saves, Eager Restores, and Greedy Shuffling (RGB, OW, RKD), pp. 130–138.

FPCA-1995-Boquist #functional #interprocedural #lazy evaluation

Interprocedural Register Allocation for Lazy Functional Languages (UB), pp. 270–281.

SAC-1995-MakowskiP #parallel #performance

Achieving efficient register allocation via parallelism (CM, LLP), pp. 123–129.

HPCA-1995-LlosaVA

Non-Consistent Dual Register Files to Reduce Register Pressure (JL, MV, EA), pp. 22–31.

HPCA-1995-NuthD #implementation #performance

The Named-State Register File: Implementation and Performance (PRN, WJD), pp. 4–13.

HPCA-1995-Weiss #implementation #multi #queue

Implementing Register Interlocks in Parallel-Pipeline Multiple Instruction Queue, Superscalar Processors (SW), pp. 14–21.

EDAC-1994-IllmanT #architecture

A Fragmented Register Architecture and Test Advisor for BIST (RI, DJT), pp. 124–129.

EDAC-1994-RamachandranK #synthesis

Incorporating the Controller Effects During Register Transfer Level Synthesis (CR, FJK), pp. 308–313.

PLDI-1994-NorrisP #dependence #graph

Register Allocation over the Program Dependence Graph (CN, LLP), pp. 266–277.

PLDI-1993-KolteH #analysis

Load/Store Range Analysis for Global Register Allocation (PK, MJH), pp. 268–277.

PLDI-1993-Pinter #approach #scheduling

Register Allocation with Instruction Scheduling: A New Approach (SSP), pp. 248–257.

PLILP-1993-KesslerR #performance #scalability

Efficient Register Allocation for Large Basic Blocks (CWK, TR), pp. 418–419.

POPL-1993-Adl-TabatabaiG #debugging #interactive

Evicted Variables and the Interaction of Global Register Allocation and Symbolic Debugging (ARAT, TRG), pp. 371–383.

POPL-1993-NingG #framework #novel #pipes and filters

A Novel Framework of Register Allocation for Software Pipelining (QN, GRG), pp. 29–42.

PLDI-1992-ProebstingF

Probalistic Register Allocation (TAP, CNF), pp. 300–310.

PLDI-1992-RauLTS #pipes and filters

Register Allocation for Software Pipelined Loops (BRR, ML, PPT, MSS), pp. 283–299.

CC-1992-DuesterwaldGS #approach #pipes and filters

Register Pipelining: An Integrated Approach to Register Allocation for Scalar and Subscripted Variables (ED, RG, MLS), pp. 192–206.

CC-1992-HendrenGAM #framework #graph

A Register Allocation Framework Based on Hierarchical Cyclic Interval Graphs (LJH, GRG, ERA, CM), pp. 176–191.

PLDI-1991-CallahanK #graph

Register Allocation via Hierarchical Graph Coloring (DC, BK), pp. 192–203.

PLILP-1991-KeslerPR #approach #heuristic #random

A Randomized Heuristic Approach to Register Allocation (CWK, WJP, TR), pp. 195–206.

ASPLOS-1991-BradleeEH #scheduling

Integrating Register Allocation and Instruction Scheduling for RISCs (DGB, SJE, RRH), pp. 122–131.

ASPLOS-1991-Mangione-SmithAD #design #scheduling

Vector Register Design for Polycyclic Vector Scheduling (WHMS, SGA, ESD), pp. 154–163.

ICLP-1991-MatyskaJT

Register Allocation in WAM (LM, AJ, DT), pp. 142–156.

DAC-1990-GhoshDN90a #generative #logic #testing

Sequential Test Generation at the Register-Transfer and Logic Levels (AG, SD, ARN), pp. 580–586.

DAC-1990-Woo #synthesis

A Global, Dynamic Register Allocation and Binding for a Data Path Synthesis System (NSW), pp. 505–510.

PLDI-1990-CallahanCK

Improving Register Allocation for Subscripted Variables (DC, SC, KK), pp. 53–65.

PLDI-1990-Nickerson #graph #multi

Graph Coloring Register Allocation for Processors with Multi-Register Operands (BRN), pp. 40–52.

PLDI-1990-SanthanamO #bound

Register Allocation Across Procedure and Module Boundaries (VS, DO), pp. 28–39.

Best-of-PLDI-1990-CallahanCK90a

Improving register allocation for subscripted variables (with retrospective) (DC, SC, KK), pp. 328–342.

PPoPP-1990-Gupta #parallel

Employing Register Channels for the Exploitation of Instruction Level Parallelism (RG), pp. 118–127.

CAV-1990-NakamuraKFT #logic #using #verification

A Data Path Verifier for Register Transfer Level Using Temporal Logic Language Tokio (HN, YK, MF, HT), pp. 76–85.

DAC-1989-GoossensVM #optimisation #scheduling

Loop Optimization in Register-Transfer Scheduling for DSP-Systems (GG, JV, HDM), pp. 826–831.

DAC-1989-Knapp #interactive #optimisation

An Interactive Tool for Register-level Structure Optimization (DK), pp. 598–601.

PLDI-1989-BriggsCKT #heuristic

Coloring Heuristics for Register Allocation (PB, KDC, KK, LT), pp. 275–284.

PLDI-1989-ChiD #liveness #using

Unified Management of Registers and Cache Using Liveness and Cache Bypass (CHC, HGD), pp. 344–355.

PLDI-1989-GuptaSS #clique

Register Allocation via Clique Separators (RG, MLS, TS), pp. 264–274.

Best-of-PLDI-1989-BriggsCKT89a #heuristic

Coloring heuristics for register allocation (with retrospective) (PB, KDC, KK, LT), pp. 283–294.

ICALP-1989-MehlhornP #source code

Two Versus One Index Register and Modifiable Versus Non-modifiable Programs (KM, WJP), pp. 603–609.

ASPLOS-1989-Karger #performance #using

Using Registers to Optimize Cross-Domain Call Performance (PAK), pp. 194–204.

PLDI-1988-Chow

Minimizing Register Usage Penalty at Procedure Calls (FCC), pp. 85–94.

PLDI-1988-Wall

Register Windows versus Register Allocation (DWW), pp. 67–78.

STOC-1988-Ben-OrC #algebra #constant #using

Computing Algebraic Formulas Using a Constant Number of Registers (MBO, RC), pp. 254–257.

Best-of-PLDI-1988-Wall88a

Register windows vs. register allocation (with retrospective) (DWW), pp. 270–282.

JICSCP-1988-JanssensDM88 #unification

Improving the Register Allocation of WAM by Recording Unification (GJ, BD, AM), pp. 1388–1402.

HCI-SES-1987-Rahav

Computerization of Psychiatric Case Registers: Public Peril vs. Hazards to Confidentiality (MR), pp. 25–30.

Best-of-PLDI-1986-Wall

Global register allocation at link time (with retrospective) (DWW), pp. 192–204.

SLP-1986-Debray86 #prolog

Register Allocation in a Prolog Machine (SKD), pp. 267–275.

DAC-1985-ShteingartNG #automation #generative #named

RTG: automatic register level test generator (SS, AWN, JG), pp. 803–807.

DAC-1984-ParkerKM #design #synthesis #verification

A general methodology for synthesis and verification of register-transfer designs (ACP, FJK, MJM), pp. 329–335.

SCC-1984-ChowH

Register allocation by priority-based coloring (FCC, JLH), pp. 222–232.

Best-of-PLDI-1984-ChowH

Register allocation by priority-based coloring (with retrospective) (FCC, JLH), pp. 91–103.

DAC-1983-GranackiP #design #performance #trade-off

The effect of register-transfer design tradeoffs on chip area and performance (JJG, ACP), pp. 419–424.

SCC-1982-Chaitin #graph

Register Allocation & Spilling via Graph Coloring (GJC), pp. 98–105.

Best-of-PLDI-1982-Chaitin #graph

Register allocation and spilling via graph coloring (with retrospective) (GJC), pp. 66–74.

ASPLOS-1982-DitzelM #c #for free #stack

Register Allocation for Free: The C Machine Stack Cache (DRD, HRM), pp. 48–56.

DAC-1981-HaferP #analysis #design #formal method #logic #specification

A formal method for the specification, analysis, and design of register-transfer level digital logic (LJH, ACP), pp. 846–853.

SCC-1979-Sites #independence

Machine-independent register allocation (RLS), pp. 221–225.

DAC-1978-HaferP #automation #design #process

Register-transfer level digital design automation: The allocation process (LJH, ACP), pp. 213–219.

VLDB-1977-Kluge

Data File Management in Shift Register Memories (WEK), pp. 211–212.

STOC-1973-Sethi #problem

Complete Register Allocation Problems (RS), pp. 182–195.

STOC-1972-Sethi #source code #validation

Validating Register Allocations for Straight Line Programs (RS), pp. 222–237.