Koji Inoue, Koji Kai, Kazuaki Murakami
Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs
HPCA, 1999.
@inproceedings{HPCA-1999-InoueKM,
author = "Koji Inoue and Koji Kai and Kazuaki Murakami",
booktitle = "{Proceedings of the Fifth International Symposium on High-Performance Computer Architecture}",
doi = "10.1109/HPCA.1999.744366",
isbn = "0-7695-0004-8",
pages = "218--222",
publisher = "{IEEE Computer Society}",
title = "{Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs}",
year = 1999,
}