Proceedings of the Fifth International Symposium on High-Performance Computer Architecture
HPCA, 1999.

@proceedings{HPCA-1999,
	address       = "Orlando, Florida, USA",
	ee            = "http://www.computer.org/csdl/proceedings/hpca/1999/0004/00/index.html",
	isbn          = "0-7695-0004-8",
	publisher     = "{IEEE Computer Society}",
	title         = "{Proceedings of the Fifth International Symposium on High-Performance Computer Architecture}",
	year          = 1999,
}

Contents (39 items)

11 ×#memory management
10 ×#performance
8 ×#multi
6 ×#named
6 ×#parallel
5 ×#thread
4 ×#scalability
3 ×#design
3 ×#distributed
2 ×#architecture

HPCA-1999-NakraGS #predict

Global Context-Based Value Prediction (TN, RG, MLS), pp. 4–12.

HPCA-1999-BrooksM #performance

Dynamically Exploiting Narrow Width Operands to Improve Processor Power and Performance (DMB, MM), pp. 13–22.

HPCA-1999-DurbhakulaPA #multi #simulation #trade-off

Improving the Accuracy vs. Speed Tradeoff for Simulating Shared-Memory Multiprocessors with ILP Processors (MD, VSP, SVA), pp. 23–32.

HPCA-1999-GatlinC #memory management #performance

Memory Hierarchy Considerations for Fast Transpose and Bit-Reversals (KSG, LC), pp. 33–42.

HPCA-1999-WallaceTC #multi

Instruction Recycling on a Multiple-Path Processor (SW, DMT, BC), pp. 44–53.

HPCA-1999-TullsenLEL #fine-grained #multi #thread

Supporting Fine-Grained Synchronization on a Simultaneous Multithreading Processor (DMT, JLL, SJE, HML), pp. 54–58.

HPCA-1999-ParcerisaG #multi #thread

The Synergy of Multithreading and Access/Execute Decoupling (JMP, AG), pp. 59–63.

HPCA-1999-HilyS #effectiveness #execution #multi #thread

Out-of-Order Execution may not be Cost-Effective on Processors Featuring Simultaneous Multithreading (SH, AS), pp. 64–67.

HPCA-1999-CarterHSSZBDKKPST #memory management #named

Impulse: Building a Smarter Memory Controller (JBC, WCH, LS, MRS, LZ, EB, AD, CCK, RK, MAP, LS, TT), pp. 70–79.

HPCA-1999-HongMSKAW #effectiveness #memory management #order

Access Order and Effective Bandwidth for Streams on a Direct Rambus Memory (SIH, SAM, MHS, RHK, JHA, WAW), pp. 80–89.

HPCA-1999-TanakaMH #distributed #hardware #lightweight #memory management

Lightweight Hardware Distributed Shared Memory Supported by Generalized Combining (KT, TM, KH), pp. 90–99.

HPCA-1999-HuangL #locality #reuse

Exploiting Basic Block Value Locality with Block Reuse (JH, DJL), pp. 106–114.

HPCA-1999-RotenbergJS #case study #independence

A Study of Control Independence in Superscalar Processors (ER, QJ, JES), pp. 115–124.

HPCA-1999-JacobsonS #preprocessor

Instruction Pre-Processing in Trace Processors (QJ, JES), pp. 125–129.

HPCA-1999-FernandesLT #distributed #scheduling

Distributed Modulo Scheduling (MMF, JL, NPT), pp. 130–134.

HPCA-1999-ZhangRT #hardware #parallel

Hardware for Speculative Parallelization of Partially-Parallel Loops in DSM Multiprocessors (YZ, LR, JT), pp. 135–139.

HPCA-1999-MichaelN #design #memory management #multi #performance #scalability

Design and Performance of Directory Caches for Scalable Shared Memory Multiprocessors (MMM, AKN), pp. 142–151.

HPCA-1999-IyerB #framework #latency #memory management #multi

Switch Cache: A Framework for Improving the Remote Memory Access Latency of CC-NUMA Multiprocessors (RRI, LNB), pp. 152–160.

HPCA-1999-KaxirasG #performance #predict #using

Improving CC-NUMA Performance Using Instruction-Based Prediction (SK, JRG), pp. 161–170.

HPCA-1999-HagerstenK #named #scalability

WildFire: A Scalable Path for SMPs (EH, MK), pp. 172–181.

HPCA-1999-FalsafiW #abstraction #communication #parallel #programming #protocol #queue

Parallel Dispatch Queue: A Queue-Based Programming Abstraction to Parallelize Fine-Grain Communication Protocols (BF, DAW), pp. 182–192.

HPCA-1999-BilasJZS #approach #memory management #performance

Limits to the Performance of Software Shared Memory: A Layered Approach (AB, DJ, YZ, JPS), pp. 193–202.

HPCA-1999-HuYN #named #reliability

RAPID-Cache — A Reliable and Inexpensive Write Cache for Disk I/O Systems (YH, QY, TN), pp. 204–213.

HPCA-1999-SchwarzSB #development #layout #permutation

Permutation Development Data Layout (PDDL) (TJES, JS, WAB), pp. 214–217.

HPCA-1999-InoueKM #logic #memory management

Dynamically Variable Line-Size Cache Exploiting High On-Chip Memory Bandwidth of Merged DRAM/Logic LSIs (KI, KK, KM), pp. 218–222.

HPCA-1999-RheeL #network #scalability

A Scalable Cache Coherent Scheme Exploiting Wormhole Routing Networks (YR, JL), pp. 223–226.

HPCA-1999-PirvuBN #performance

The Impact of Link Arbitration on Switch Performance (MP, LNB, NN), pp. 228–235.

HPCA-1999-VaidyaSD #adaptation #design #named #performance

LAPSES: A Recipe for High Performance Adaptive Router Design (ASV, AS, CRD), pp. 236–243.

HPCA-1999-PlaatBH #difference #latency #parallel #scalability

Sensitivity of Parallel Applications to Large Differences in Bandwidth and Latency in Two-Layer Interconnects (AP, HEB, RFHH), pp. 244–253.

HPCA-1999-DwarkadasGKSSS #comparative #distributed #evaluation #memory management

Comparative Evaluation of Fine- and Coarse-Grain Approaches for Software Distributed Shared Memory (SD, KG, LIK, DJS, MLS, RS), pp. 260–269.

HPCA-1999-CondonHPS #memory management #modelling #using

Using Lamport Clocks to Reason about Relaxed Memory Models (AC, MDH, MP, DJS), pp. 270–278.

HPCA-1999-CoxLHZ #comparison #consistency #lazy evaluation #memory management #performance #protocol

A Performance Comparison of Homeless and Home-Based Lazy Release Consistency Protocols in Software Shared Memory (ALC, EdL, YCH, WZ), pp. 279–283.

HPCA-1999-KuoCK #message passing #named

MP-LOCKs: Replacing H/W Synchronization Primitives with Message Passing (CCK, JBC, RK), pp. 284–288.

HPCA-1999-YangW #network #performance

Efficient All-to-All Broadcast in All-Port Mesh and Torus Networks (YY, JW), pp. 290–299.

HPCA-1999-DuatoYCLQ #architecture #design #multi #named #trade-off

MMR: A High-Performance Multimedia Router — Architecture and Design Trade-Offs (JD, SY, BC, DSL, FJQ), pp. 300–309.

HPCA-1999-SohnPKKY #communication #parallel #thread

Communication Studies of Single-Threaded and Multithreaded Distributed-Memory Multiprocessors (AS, YP, JYK, YK, YY), pp. 310–314.

HPCA-1999-MartinezLD #concurrent #detection #performance

Impact of Buffer Size on the Efficiency of Deadlock Detection (JMM, PL, JD), pp. 315–318.

HPCA-1999-KergommeauxDG #parallel

Parallel Computing for Irregular Applications (JCdK, YD, TG), p. 321.

HPCA-1999-TullsenG #architecture #compilation #execution #parallel #thread

Multithreaded Execution Architecture and Compilation (DMT, GRG), p. 321.