BibSLEIGH
BibSLEIGH corpus
BibSLEIGH tags
BibSLEIGH bundles
BibSLEIGH people
EDIT!
CC-BY
Open Knowledge
XHTML 1.0 W3C Rec
CSS 2.1 W3C CanRec
email twitter
Travelled to:
1 × Korea
Collaborated with:
G.Rodríguez-Verján E.Tartiere J.Pinaton S.Dauzère-Pérès
Talks about:
semiconductor (1) manufactur (1) dispatch (1) wafer (1) reduc (1) dynam (1) risk (1) lot (1)

Person: Alexis Thieullen

DBLP DBLP: Thieullen:Alexis

Contributed to:

CASE 20122012

Wrote 1 papers:

CASE-2012-Rodriguez-VerjanTPDT
Dispatching of lots to dynamically reduce the wafers at risk in semiconductor manufacturing (GRV, ET, JP, SDP, AT), pp. 920–923.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.