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Travelled to:
1 × Korea
Collaborated with:
G.Rodríguez-Verján J.Pinaton S.Dauzère-Pérès A.Thieullen
Talks about:
semiconductor (1) manufactur (1) dispatch (1) wafer (1) reduc (1) dynam (1) risk (1) lot (1)

Person: Eric Tartiere

DBLP DBLP: Tartiere:Eric

Contributed to:

CASE 20122012

Wrote 1 papers:

CASE-2012-Rodriguez-VerjanTPDT
Dispatching of lots to dynamically reduce the wafers at risk in semiconductor manufacturing (GRV, ET, JP, SDP, AT), pp. 920–923.
Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.