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Used together with:
size (8)
problem (4)
schedul (4)
genet (3)
semiconductor (3)

Stem lot$ (all stems)

15 papers:

FSEFSE-2014-Wille #approach #modelling
Managing lots of models: the FaMine approach (DW), pp. 817–819.
SACSAC-2013-ToledoAOD #algorithm #hybrid #multi #problem #search-based
A hybrid compact genetic algorithm applied to the multi-level capacitated lot sizing problem (CFMT, MdSA, RRRdO, ACBD), pp. 200–205.
CASECASE-2012-Rodriguez-VerjanTPDT
Dispatching of lots to dynamically reduce the wafers at risk in semiconductor manufacturing (GRV, ET, JP, SDP, AT), pp. 920–923.
CASECASE-2011-KimL #clustering #constraints #scheduling #tool support
Scheduling of cluster tools with ready time constraints for small lot production (HJK, TEL), pp. 96–101.
ICEISICEIS-v3-2011-HuaQL #order
Optimal Order Lot Sizing and Pricing with Carbon Trade (GH, HQ, JL), pp. 533–536.
SACSAC-2010-ToledoOOP #algorithm #parallel #problem #scheduling #search-based
Parallel genetic algorithm approaches applied to solve a synchronized and integrated lot sizing and scheduling problem (CFMT, LdO, RRRdO, MRP), pp. 1148–1152.
ICSEICSE-2010-ClassenHSLR #model checking #performance #product line #verification
Model checking lots of systems: efficient verification of temporal properties in software product lines (AC, PH, PYS, AL, JFR), pp. 335–344.
CASECASE-2009-Morrison #clustering #modelling #process #tool support
Regular flow line models for semiconductor cluster tools: A case of lot dependent process times (JRM), pp. 561–566.
CASECASE-2009-WuS #heuristic #multi #problem
A new heuristic method for capacitated multi-level lot sizing problem with backlogging (TW, LS), pp. 483–488.
CASECASE-2008-MatsumotoUOI #analysis #empirical #process
Business process analysis to obtain empirical lot sizing rule in printing process (SM, NU, KO, HI), pp. 591–596.
SACSAC-2008-ToledoFR #algorithm #problem #scheduling #search-based
Evaluating genetic algorithms with different population structures on a lot sizing and scheduling problem (CFMT, PMF, KAR), pp. 1777–1781.
CASECASE-2007-HuangLF #scheduling
Lot Dispatching and Scheduling Integrating OHT Traffic Information in the 300mm Wafer Fab (HWH, CHL, LCF), pp. 495–500.
CASECASE-2007-SchmidtR #queue
Queue time and x-factor characteristics for semiconductor manufacturing with small lot sizes (KS, OR), pp. 1069–1074.
ICPRICPR-v3-2004-ForestiMS #automation #classification
Event Classification for Automatic Visual-based Surveillance of Parking Lots (GLF, CM, LS), pp. 314–317.
SACSAC-2001-LeeGA #learning #multi
A multi-neural-network learning for lot sizing and sequencing on a flow-shop (IL, JNDG, ADA), pp. 36–40.

Bibliography of Software Language Engineering in Generated Hypertext (BibSLEIGH) is created and maintained by Dr. Vadim Zaytsev.
Hosted as a part of SLEBOK on GitHub.